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Xilinx Zynq UltraScale+ ZCU208 - Page 31

Xilinx Zynq UltraScale+ ZCU208
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The following gure shows a high-level view of the I2C0 bus connecvity.
Figure 7: I2C0 Bus Topology
TCA6416A
P00
P01
P02
P04
P05
P06
P07
MAX6643_OT_B
MAX6643_FANFAIL_B
MI026_PMU_INPUT_LS
DAC_AVTT_VOUT_SEL
IIC_MUX_RESET_B
GEM3_EXP_RESET_B
MAX6643_FULL_SPEED
SDA/
SCL
BANK 500
PS I2C0
MIO15/
MIO14
U1
BANK 89
PL I2C0
C11/B11
U1
MPS430
U38
22 P3_0
23 P3_1
L/S
U13
0x20
P10
P11
P12
P16
P17
FMC_HSPC_PRSNT_M2C_B
CLK_SPI_MUX_SEL0
CLK_SPI_MUX_SEL1
IRPS5401_ALERT_B
INA226_PMBUS_ALERT
U14
PCA9544A
SDA/
SCL
0x75
INA226_PMBUS_SCA/SCL
Not Connected
IRPS5401_PMBUS_SDA/SCL
SYSMON_SCA/SCL
U17
SD0/SC0
SD1/SC1
SD2/SC2
SD3/SC3
U15
I2C0_SDA/SCL
L/S
X23644-012120
The following table
idenes the devices on each port of the I2C0 U15 TCA6416A port
expander.
Table 9: I2C0 Port Expander TCA6416A U15 Connections
TCA6416A U15
Schematic Net Name
Connected To
Pin
Name
Pin No. Pin No. Pin Name
Reference
Designator
Device
SDA 23 I2C0_SDA Refer to connections shown in the figure above.
TCA6416A U15 Addr. 0x20
SCL 22 I2C0_SCL
P00 4 MAX6643_OT_B 9 OT_B U50 MAX6643
Chapter 3: Board Component Descriptions
UG1410 (v1.0) July 8, 2020 www.xilinx.com
ZCU208 Board User Guide 31
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