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Xilinx Zynq UltraScale+ ZCU208 - Page 89

Xilinx Zynq UltraScale+ ZCU208
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Figure 42: High ADCIO and DACIO Digital I/O Header Pins
Appendix C: HW-XM650/655 Balun Daughter Cards for Gen 3 RFSoC EVM
UG1410 (v1.0) July 8, 2020 www.xilinx.com
ZCU208 Board User Guide 89
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