IEC09000310 V1 EN
Figure 129: Example designation, serial execution number and cycle time for logic
function that also propagates timestamp and quality of input signals
The execution of different function blocks within the same cycle is determined by the
order of their serial execution numbers. Always remember this when connecting two or
more logical function blocks in series.
Always be careful when connecting function blocks with a fast cycle time
to function blocks with a slow cycle time.
Remember to design the logic circuits carefully and always check the
execution sequence for different functions. In other cases, additional time
delays must be introduced into the logic schemes to prevent errors, for
example, race between functions.
Default value on all four inputs of the AND and ANDQT gate are logical
1 which makes it possible for the user to just use the required number of
inputs and leave the rest un-connected. The output OUT has a default
value 0 initially, which will suppress one cycle pulse if the function has
been put in the wrong execution order.
11.4 Fixed signals FXDSIGN
11.4.1 Identification
Function description
IEC 61850
identification
IEC 60617
identification
ANSI/IEEE C37.2
device number
Fixed signals FXDSIGN - -
Section 11 1MRK 511 286-UUS A
Logic
276
Application manual
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