Advantech AIMB-501 - DMA Channel Assignments; Interrupt Assignments; Table B.26:DMA Channel Assignments; B.27 Interrupt Assignments

99 AIMB-501 User Manual
Appendix B I/O Pin Assignments
B.26 DMA Channel Assignments
B.27 Interrupt Assignments
B.28 1st MB Memory Map
Table B.26: DMA Channel Assignments
Channel Function
0 Available
1 Available
2 Available
3 ECP Printer Port (LPT1)
4 Cascade for DMA controller 1
5 Available
6 Available
7 Available
Table B.27: Interrupt Assignments
Priority Interrupt# Interrupt source
1 NMI Parity error detected
2 IRQ0 Interval timer
3 IRQ1 Keyboard
- IRQ2 Interrupt from controller 2 (cascade)
4 IRQ8 Real-time clock
5 IRQ9 Cascaded to INT 0A (IRQ 2)
6 IRQ10 Serial communication port 3/4/5/6
7 IRQ11 Serial communication port 7/8/9/10
8 IRQ12 PS/2 mouse
9 IRQ13 INT from co-processor
10 IRQ14 Primary IDE Channel
11 IRQ15 Secondary IDE Channel
12 IRQ3 Serial communication port 2
13 IRQ4 Serial communication port 1
14 IRQ5 Available
15 IRQ6 Available
16 IRQ7 Parallel port 1 (print port)
Table B.28: 1st MB Memory Map
Addr. range (Hex) Device
E0000h - FFFFFh BIOS
CC000h - DFFFFh Unused
C0000h - CBFFFh VGA BIOS
A0000h - BFFFFh Video Memory
00000h - 9FFFFh Base memory