Altera Corporation 19
Nios Development Board Reference Manual, Cyclone Edition Board Components
Figure 4. Ethernet MAC/PHY Device
The Ethernet MAC/PHY device share address and data connections with
the flash memory and the SRAM chips. For shared bus information, see
“Appendix A: Shared Bus Table” on page 39.
f
See www.smsc.com for detailed information about the LAN91C111
device. See the Plugs Ethernet Library Reference Manual for details on
accessing the MAC/PHY device in Nios software.
Expansion
Prototype
Connector
(PROTO1)
The PROTO1 expansion prototype connectors share Cyclone IO pins with
the compact flash connector. Designs may use either the PROTO1
connectors or the compact flash.
Headers J11, J12, and J13 collectively form the standard-footprint,
mechanically-stable connection that can be used (for example) as an
interface to a special-function daughter card.
1 See the Altera web site for a list of available expansion daughter
cards that can be used with the Nios development board at
www.altera.com/devkits.
The expansion prototype connector interface includes:
■ 41 I/O pins for prototyping. All 41 I/O pins connect to user I/O pins
on the Cyclone device. Each signal passes through analog switches
(U19, U20, U21, U22 and U25) to protect the Cyclone device from 5-V
logic levels. These analog switches are permanently enabled.
■ A buffered, zero-skew copy of the on-board OSC output from U2.
■ A buffered, zero-skew copy of the Cyclone's phase-locked loop
(PLL)-output from U60.
■ A logic-negative power-on reset signal
■ Five regulated 3.3-V power-supply pins (2A total max load for both
PROTO1 & PROTO2)
■ One regulated 5-V power-supply pin (1A total max load for both
PROTO1 & PROTO2)
■ Numerous ground connections
The output logic level on the expansion prototype connector pins is 3.3V.
The power supply included wit the Nios development kit cannot supply
the maximum load current specified above.
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