Altera Corporation 39
Appendix A
2
On the Nios Development Board, Cyclone Edition, the flash memory, SRAM and Ethernet
MAC/PHY devices share address and control lines. These shared lines are referred to as the Shared
Bus. Using SOPC Builder, designers can interface a Nios processor system to any device connected
to the off-chip shared bus.
Table 12 on page 40 lists all connections between the devices connected to the shared bus.
Appendix A:
Shared Bus Table
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