Altera Nios - Index

Altera Corporation 49
Index
5
A
Appendix A
Shared bus table 39
Appendix B
Restore the factory configuration 43
Appendix C
Board Ethernet connection 45
B
Block diagram 11
Board Ethernet connection
Browse the board 48
Connecting the Ethernet cable 45
Connecting the LCD display 46
Obtaining an IP address - DHCP 46
LAN connections 48
Point-to-point connections 47
C
Clock circuitry 35
Compact flash connector 14
Configuration and reset buttons 33
SW10 - Reset config 34
SW8 - CPU reset 34
SW9 - Safe config 34
Configuration controller device 28
Configuration data 29
Configuration-status LEDs 33
Cyclone configuration 28
Reset distribution 28
Safe and user configurations 30
Starting configuration 28
Configuration-status LEDs
Indicators 33
Conventional flash memory usage 30
Cyclone EP1C20 device 13
D
Development board
Component illustration 12
Features 9
General description 9
Dual 7-segment display 26
U8 & U9 pin information 26
Dual SRAM devices 18
E
Ethernet PHY/MAC 19
Expansion connector header (PROTO1) 19
J11 pin information 20
J12 pin information 21
J13 pin information 21
Expansion connector header (PROTO2) 21
J15 pin information 23
J16 pin information 22
J17 pin out information 23
F
Flash memory allocation 31
Flash memory device 13
I
Individual LEDs (D0 - D7) 27
Pin information 27
J
JTAG connections 36
JTAG to Cyclone device (J24) 36
JTAG to MAX device (J5) 38
Index