Altera Nios - Page 42

42 Altera Corporation
Shared Bus Table Nios Development Board Reference Manual, Cyclone Edition
FLASH_CS_n
Chip Select
IO A12
CE_n
28
FLASH_OE-N
Read Enable
IO B12
OE_n
30
FLASH_RW-N
Write Enable
IO D12
WE_n
11
FLASH_RY-BY_N
Ready/Busy
IO C12
RY/BY_n
14
SRAM_BE_N0
Byte Enable 0
IO V17 BE0# 39
SRAM_BE_N1
Byte Enable 1
IO V16 BE1# 40
SRAM_BE_N2
Byte Enable 2
IO W16 BE2# 39
SRAM_BE_N3
Byte Enable 3
IO T16 BE3# 40
SRAM_CS_N
Chip Select
IO W17 CS_n 6 CS_n 6
SRAM_OE_N
Read Enable
IO Y17 OE_n 41 OE_n 41
SRAM_WE_N
Write Enable
IO U16 WE_n 17 WE_n 17
ENET_ADS_N
Address Strobe
IO A14
ADS#
37
ENET_AEN
Address Enable
IO B15
AEN
41
ENET_BE_N0
Byte Enable 0
IO C16
BE0#
94
ENET_BE_N1
Byte Enable 1
IO B16
BE1#
95
ENET_BE_N2
Byte Enable 2
IO D16
BE2#
96
ENET_BE_N3
Byte Enable 3
IO E16
BE3#
97
ENET_CYCLE_N
Bus Cycle
IO B17
CYCLE#
35
ENET_DATACS_N
Data Chip
Select
IO C15
DATACS#
34
ENET_INTRQ0
Interrupt
IO D15
INTRO
29
ENET_IOCHRDY
IO Char Ready
IO F14
ARDY
38
ENET_IOR_N
Read
IO A15
RD#
31
ENET_IOW_N
Write
IO E15
WR#
32
ENET_LCLK
Local Bus
Clock
IO C17
LCLK
42
ENET_LDEV_N
Local Device
IO D3
LDEV#
45
ENET_RDYRTN_N
Ready Return
IO B18
RDYRTN#
46
ENET_W_R_N
Write/Read
IO A17
W/R#
36
Table 12. Shared Bus Table (Part 3 of 3)
NET Name NET
Description
PLD (U60) Flash (U5) SRAM (U35) SRAM (U36) Ethernet (U4)