AMD VCU118 - Appendix B: Xilinx Constraints File; Overview

VCU118 Board User Guide 116
UG1224 (v1.5) March 15, 2023
Appendix B
Xilinx Constraints File
Overview
The Xilinx design constraints (XDC) file template for the VCU118 board provides for designs
targeting the VCU118 evaluation board. Net names in the constraints correlate with net
names on the latest VCU118 evaluation board schematic. Users must identify the
appropriate pins and replace the net names with net names in the user RTL. See the Vivado
Design Suite User Guide: Using Constraints (UG903) [Ref 11] for more information.
The FMC connectors J22 (FMCP) and J2 (FMC HPC1) are connected to 1.8V VADJ banks.
Because different FMC cards implement different circuitry, the FMC bank I/O standards
must be uniquely defined by each customer.
IMPORTANT: The XDC file can be accessed on the VCU118 Evaluation Kit website.
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