VCU118 Board User Guide 31
UG1224 (v1.5) March 15, 2023
Chapter3: Board Component Descriptions
The VCU118 dual DDR4 80-bit memory component interfaces adhere to the constraints
guidelines documented in the “DDR3/DDR4 Design Guidelines” section of the UltraScale
Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150) [Ref 4]. The
VCU118 board DDR4 memory component interface is a 40 impedance implementation.
For more information on the internal VREF, see the “Supply Voltages for the SelectIO Pins
VREF” and the “Internal VREF” sections in the UltraScale Architecture SelectIO Resources User
Guide (UG571) [Ref 3]. For more details about the Micron DDR4 component memory, see
the Micron MT40A256M16GE data sheet at the Micron website [Ref 18].
RLD3 Component Memory
[Figure 2-1, callout 5]
The 288 MB RLD3 72-bit wide component memory system is comprised of two 36-bit
1.125 Gb RLDRAM3 devices located at U141-U142.
• Manufacturer: Micron
• Part Number: MT44K32M36RB-093E
•Description:
°
1.125 Gb (32 Mb x 36 CIO)
°
1.35V 168-ball BGA
°
RL3-2133 (1200 MHz DDR operation)
The VCU118 XCVU9P RLDRAM3 interface performance is documented in the Virtex
UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS923) [Ref 1].
This memory system is connected to the XCVU9P HP banks 46, 47, and 48.
The RLD3 0.6V V
TT
termination voltage (net RLD3_C3_VTT) is sourced from TI TPS51200DR
linear regulator U143. The RLD3 memory interface bank VREF pins are not connected,
which, coupled with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL
VREF mode. The connections between the RLD3 component memories and XCVU9P banks
46, 47, and 48 are listed in Table 3-4.
BB29 DDR4_C2_ODT SSTL12_DCI T3 PAR U135-U139
AY29 DDR4_C2_CS_B SSTL12_DCI K3 ODT U135-U139
AR29 DDR4_C2_ALERT_B SSTL12_DCI L7 CS_B U135-U139
BD35 DDR4_C2_RESET_B LVCMOS12 P1 RESET_B U135-U139
AY35 DDR4_C2_TEN SSTL12_DCI N9 TEN U135-U139
Table3‐3: DDR4 Memory 80‐bit I/F C2 to FPGA U1 Banks 40, 41, and 42 (Cont’d)
FPGA (U1)
Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
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