AMD VCU118 - Page 32

VCU118 Board User Guide 32
UG1224 (v1.5) March 15, 2023
Chapter3: Board Component Descriptions
Table3‐4: RLD3 Memory 72‐bit I/F to FPGA U1 Banks 46, 47, and 48
FPGA
(U1) Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
H39 RLD3_C3_72B_DQ0 SSTL12 D11 DQ0 U141
H40 RLD3_C3_72B_DQ1 SSTL12 E10 DQ1 U141
G40 RLD3_C3_72B_DQ2 SSTL12 C8 DQ2 U141
F40 RLD3_C3_72B_DQ3 SSTL12 C10 DQ3 U141
H38 RLD3_C3_72B_DQ4 SSTL12 C12 DQ4 U141
G38 RLD3_C3_72B_DQ5 SSTL12 B9 DQ5 U141
K37 RLD3_C3_72B_DQ6 SSTL12 B11 DQ6 U141
J37 RLD3_C3_72B_DQ7 SSTL12 A8 DQ7 U141
F38 RLD3_C3_72B_DQ8 SSTL12 A10 DQ8 U141
J35 RLD3_C3_72B_DQ9 SSTL12 J10 DQ9 U141
H35 RLD3_C3_72B_DQ10 SSTL12 K11 DQ10 U141
J36 RLD3_C3_72B_DQ11 SSTL12 K13 DQ11 U141
H37 RLD3_C3_72B_DQ12 SSTL12 L8 DQ12 U141
H34 RLD3_C3_72B_DQ13 SSTL12 L10 DQ13 U141
G35 RLD3_C3_72B_DQ14 SSTL12 L12 DQ14 U141
F35 RLD3_C3_72B_DQ15 SSTL12 M9 DQ15 U141
F36 RLD3_C3_72B_DQ16 SSTL12 M11 DQ16 U141
G36 RLD3_C3_72B_DQ17 SSTL12 N8 DQ17 U141
E37 RLD3_C3_72B_DQ18 SSTL12 D3 DQ18 U141
E38 RLD3_C3_72B_DQ19 SSTL12 E4 DQ19 U141
C39 RLD3_C3_72B_DQ20 SSTL12 C6 DQ20 U141
B40 RLD3_C3_72B_DQ21 SSTL12 C4 DQ21 U141
A39 RLD3_C3_72B_DQ22 SSTL12 C2 DQ22 U141
A40 RLD3_C3_72B_DQ23 SSTL12 B5 DQ23 U141
D40 RLD3_C3_72B_DQ24 SSTL12 B3 DQ24 U141
C40 RLD3_C3_72B_DQ25 SSTL12 A6 DQ25 U141
B38 RLD3_C3_72B_DQ26 SSTL12 A4 DQ26 U141
D35 RLD3_C3_72B_DQ27 SSTL12 J4 DQ27 U141
C35 RLD3_C3_72B_DQ28 SSTL12 K3 DQ28 U141
D34 RLD3_C3_72B_DQ29 SSTL12 K1 DQ29 U141
C34 RLD3_C3_72B_DQ30 SSTL12 L6 DQ30 U141
B36 RLD3_C3_72B_DQ31 SSTL12 L4 DQ31 U141
B37 RLD3_C3_72B_DQ32 SSTL12 L2 DQ32 U141
Send Feedback