AMD VCU118 - Page 33

VCU118 Board User Guide 33
UG1224 (v1.5) March 15, 2023
Chapter3: Board Component Descriptions
B35 RLD3_C3_72B_DQ33 SSTL12 M5 DQ33 U141
A36 RLD3_C3_72B_DQ34 SSTL12 M3 DQ34 U141
A34 RLD3_C3_72B_DQ35 SSTL12 N6 DQ35 U141
F39 RLD3_C3_72B_DM0 SSTL12 B7 DM0 U141
A35 RLD3_C3_72B_DM1 SSTL12 M7 DM1 U141
J39 RLD3_C3_72B_QK0_P DIFF_SSTL12 D9 QK0 U141
J40 RLD3_C3_72B_QK0_N DIFF_SSTL12 E8 QK0_B U141
F34 RLD3_C3_72B_QK1_P DIFF_SSTL12 K9 QK1 U141
E34 RLD3_C3_72B_QK1_N DIFF_SSTL12 J8 QK1_B U141
E39 RLD3_C3_72B_QK2_P DIFF_SSTL12 D5 QK2 U141
D39 RLD3_C3_72B_QK2_N DIFF_SSTL12 E6 QK2_B U141
D37 RLD3_C3_72B_QK3_P DIFF_SSTL12 K5 QK3 U141
C37 RLD3_C3_72B_QK3_N DIFF_SSTL12 J6 QK3_B U141
G37 RLD3_C3_72B_QVLD0 SSTL12 J12 QVLD0 U141
A38 RLD3_C3_72B_QVLD1 SSTL12 J2 QVLD1 U141
T24 RLD3_C3_72B_DQ36 SSTL12 D11 DQ0 U142
R24 RLD3_C3_72B_DQ37 SSTL12 E10 DQ1 U142
R27 RLD3_C3_72B_DQ38 SSTL12 C8 DQ2 U142
P27 RLD3_C3_72B_DQ39 SSTL12 C10 DQ3 U142
P25 RLD3_C3_72B_DQ40 SSTL12 C12 DQ4 U142
N25 RLD3_C3_72B_DQ41 SSTL12 B9 DQ5 U142
P26 RLD3_C3_72B_DQ42 SSTL12 B11 DQ6 U142
N27 RLD3_C3_72B_DQ43 SSTL12 A8 DQ7 U142
P24 RLD3_C3_72B_DQ44 SSTL12 A10 DQ8 U142
M25 RLD3_C3_72B_DQ45 SSTL12 J10 DQ9 U142
L26 RLD3_C3_72B_DQ46 SSTL12 K11 DQ10 U142
L28 RLD3_C3_72B_DQ47 SSTL12 K13 DQ11 U142
K28 RLD3_C3_72B_DQ48 SSTL12 L8 DQ12 U142
L24 RLD3_C3_72B_DQ49 SSTL12 L10 DQ13 U142
L25 RLD3_C3_72B_DQ50 SSTL12 L12 DQ14 U142
K26 RLD3_C3_72B_DQ51 SSTL12 M9 DQ15 U142
J26 RLD3_C3_72B_DQ52 SSTL12 M11 DQ16 U142
K27 RLD3_C3_72B_DQ53 SSTL12 N8 DQ17 U142
H27 RLD3_C3_72B_DQ54 SSTL12 D3 DQ18 U142
Table3‐4: RLD3 Memory 72‐bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont’d)
FPGA
(U1) Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
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