AMD VCU118 - Page 34

VCU118 Board User Guide 34
UG1224 (v1.5) March 15, 2023
Chapter3: Board Component Descriptions
G27 RLD3_C3_72B_DQ55 SSTL12 E4 DQ19 U142
F28 RLD3_C3_72B_DQ56 SSTL12 C6 DQ20 U142
E28 RLD3_C3_72B_DQ57 SSTL12 C4 DQ21 U142
H28 RLD3_C3_72B_DQ58 SSTL12 C2 DQ22 U142
G28 RLD3_C3_72B_DQ59 SSTL12 B5 DQ23 U142
E26 RLD3_C3_72B_DQ60 SSTL12 B3 DQ24 U142
E27 RLD3_C3_72B_DQ61 SSTL12 A6 DQ25 U142
G25 RLD3_C3_72B_DQ62 SSTL12 A4 DQ26 U142
B28 RLD3_C3_72B_DQ63 SSTL12 J4 DQ27 U142
A28 RLD3_C3_72B_DQ64 SSTL12 K3 DQ28 U142
C27 RLD3_C3_72B_DQ65 SSTL12 K1 DQ29 U142
B27 RLD3_C3_72B_DQ66 SSTL12 L6 DQ30 U142
B26 RLD3_C3_72B_DQ67 SSTL12 L4 DQ31 U142
A26 RLD3_C3_72B_DQ68 SSTL12 L2 DQ32 U142
D25 RLD3_C3_72B_DQ69 SSTL12 M5 DQ33 U142
D26 RLD3_C3_72B_DQ70 SSTL12 M3 DQ34 U142
C25 RLD3_C3_72B_DQ71 SSTL12 N6 DQ35 U142
N24 RLD3_C3_72B_DM2 SSTL12 B7 DM0 U142
B25 RLD3_C3_72B_DM3 SSTL12 M7 DM1 U142
T26 RLD3_C3_72B_QK4_P DIFF_SSTL12 D9 QK0 U142
R26 RLD3_C3_72B_QK4_N DIFF_SSTL12 E8 QK0_B U142
M27 RLD3_C3_72B_QK5_P DIFF_SSTL12 K9 QK1 U142
M28 RLD3_C3_72B_QK5_N DIFF_SSTL12 J8 QK1_B U142
G26 RLD3_C3_72B_QK6_P DIFF_SSTL12 D5 QK2 U142
F26 RLD3_C3_72B_QK6_N DIFF_SSTL12 E6 QK2_B U142
D27 RLD3_C3_72B_QK7_P DIFF_SSTL12 K5 QK3 U142
C28 RLD3_C3_72B_QK7_N DIFF_SSTL12 J6 QK3_B U142
J27 RLD3_C3_72B_QVLD2 DIFF_SSTL12 J12 QVLD0 U142
F25 RLD3_C3_72B_QVLD3 DIFF_SSTL12 J2 QVLD1 U142
A29 RLD3_C3_72B_A0 SSTL12 E2 A0 U141-U142
C29 RLD3_C3_72B_A1 SSTL12 F5 A1 U141-U142
D29 RLD3_C3_72B_A2 SSTL12 F4 A2 U141-U142
B30 RLD3_C3_72B_A3 SSTL12 F9 A3 U141-U142
C30 RLD3_C3_72B_A4 SSTL12 F10 A4 U141-U142
Table3‐4: RLD3 Memory 72‐bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont’d)
FPGA
(U1) Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
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