AMD VCU118 - Page 35

VCU118 Board User Guide 35
UG1224 (v1.5) March 15, 2023
Chapter3: Board Component Descriptions
A31 RLD3_C3_72B_A5 SSTL12 F12 A5 U141-U142
A30 RLD3_C3_72B_A6 SSTL12 G3 A6 U141-U142
A33 RLD3_C3_72B_A7 SSTL12 F1 A7 U141-U142
B33 RLD3_C3_72B_A8 SSTL12 G11 A8 U141-U142
B32 RLD3_C3_72B_A9 SSTL12 F13 A9 U141-U142
B31 RLD3_C3_72B_A10 SSTL12 H13 A10 U141-U142
C33 RLD3_C3_72B_A11 SSTL12 D1 A11 U141-U142
C32 RLD3_C3_72B_A12 SSTL12 H11 A12 U141-U142
D30 RLD3_C3_72B_A13 SSTL12 D13 A13 U141-U142
E29 RLD3_C3_72B_A14 SSTL12 H3 A14 U141-U142
F29 RLD3_C3_72B_A15 SSTL12 G2 A15 U141-U142
D32 RLD3_C3_72B_A16 SSTL12 H4 A16 U141-U142
E32 RLD3_C3_72B_A17 SSTL12 H10 A17 U141-U142
D31 RLD3_C3_72B_A18 SSTL12 G12 A18 U141-U142
E31 RLD3_C3_72B_A19 SSTL12 H1 A19 U141-U142
R28 RLD3_C3_72B_A20 SSTL12 F2 NF_A20 U141-U142
E33 RLD3_C3_72B_BA0 SSTL12 G9 BA0 U141-U142
F33 RLD3_C3_72B_BA1 SSTL12 G5 BA1 U141-U142
F30 RLD3_C3_72B_BA2 SSTL12 H8 BA2 U141-U142
G30 RLD3_C3_72B_BA3 SSTL12 H6 BA3 U141-U142
K29 RLD3_C3_72B_WE_B SSTL12 F6 WE_B U141-U142
L30 RLD3_C3_72B_REF_B SSTL12 F8 REF_B U141-U142
H29 RLD3_C3_72B_CK_P SSTL12 H7 CK U141-U142
H30 RLD3_C3_72B_CK_N SSTL12 G7 CK_B U141-U142
L29 RLD3_C3_72B_RESET_B SSTL12 A13 RESET_B U141-U142
N29 RLD3_C3_72B_CS_B SSTL12 E12 CS_B U141-U142
K31 RLD3_C3_72B_DK0_P DIFF_SSTL12 D7 DK0 U141
J31 RLD3_C3_72B_DK0_N DIFF_SSTL12 C7 DK0_B U141
K32 RLD3_C3_72B_DK1_P DIFF_SSTL12 K7 DK1 U141
J32 RLD3_C3_72B_DK1_N DIFF_SSTL12 L7 DK1_B U141
J29 RLD3_C3_72B_DK2_P DIFF_SSTL12 D7 DK0 U142
J30 RLD3_C3_72B_DK2_N DIFF_SSTL12 C7 DK0_B U142
H33 RLD3_C3_72B_DK3_P DIFF_SSTL12 K7 DK1 U142
G33 RLD3_C3_72B_DK3_N DIFF_SSTL12 L7 DK1_B U142
Table3‐4: RLD3 Memory 72‐bit I/F to FPGA U1 Banks 46, 47, and 48 (Cont’d)
FPGA
(U1) Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
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