AMLOGIC S905D3 - 5.7.9 UART Timing Specification

0.6 (2019–07–25)
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Symbol Description Min. Max. Unit
THOL Data input Hold Time 4 ns
TLH Minimum idling time
between transfers (-
minimum ss high
time)
5 ns
5.7.5 SPIFC Timing Specification
Figure 5-12 SPIFC Serial Input Timing Diagram
Figure 5-13 SPIFC Out Timing Diagram
Table 5-10 SPIFC Master Timing Specification
Symbol Parameter (Clock
41.7MHz)
Min Max Unit
fRSCLK Clock Frequency for
READ instructions
50 Mhz
tCH Clock High Time 8 ns
tCL Clock Low Time 8 ns
S905D3 Quick Reference Manual 5 Operating Conditions
Preliminary Version
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