AMLOGIC S905D3 - Power Consumption

0.6 (2019–07–25)
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65
Note
1. All test values refer to 80% of typical power voltage.
2. VDDAO_3.3V & VCC3.3V should ramp up > 0.5ms later than VDD_EE.
3. All power sources should get stable within 20ms (except for DDR_VDDQ).
4. No sequence requirement between VDDCPU & DDR_VDDQ and other power source.
5. VDDIO_AO18 should ramps up earlier than or at the same time with VDDAO_3.3V &
VCC3.3V, VDDAO_3.3V & VCC3.3V should never be 2.5V higher than VDDIO_AO18.
6. In some designs, VDDCPU & VDD_EE are merged to VCC_CORE, the power on sequence
should be same as VDD_EE.
7. RESET_n should keep low for at least 40ms after power up (except DDR_VDDQ).
Please refer to reference schematics.
5.11 Power Consumption
Note
Value listed here is estimated typical max value tested. Enough margin in circuit needs to be
reserved.
Symbol Maximum Current Note
VDDCPU 2.5 A -
VDD_EE 1.5 A -
VDD_DDR 400 mA -
VDDQ 600 mA VDDQ Maximum current does not include DRAM current.
Peak SOC + DRAM VDDQ current is up to 1.5A with 2 ranks
DDR3
Symbol Typical Current Maximum Current Note
VDD18_AO_XTAL 0.6mA 1mA EFUSE: Max 100mA when
programing EFUSE
AVDD0V8_USB_
PCIE
19.2mA 58mA -
AVDD0V8_HDMI 17.2mA 23mA At 6 Gbps mode
AVDD_DDRPLL 4.1mA 6mA -
AVDD18_ENET 35.5mA 40mA -
AVDD18_AUDIO 4mA 6.6mA -
AVDD18_PCIE 31.6mA 40mA At 5 Gbps mode(WIFI
module)
AVDD18_HDMI 9.3mA 15.3mA -
AVDD18_SARADC 2.1mA 2.5mA -
AVDD18_CVBS 39.8mA 48mA -
AVDD18_MIPIDSI 29.6mA 40mA -
AVDD18_MIPICSI 16.4mA 20mA -
S905D3 Quick Reference Manual 5 Operating Conditions
Preliminary Version
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