Andor Technology Zyla sCMOS 4.2 PLUS - 2.4 Dual Amplifier Dynamic Range; Amplifier and ADC Block Diagram

version 2.0 rev 18 Feb 2021
24
2.4  DualAmplierDynamicRange
TheDualAmplierarchitectureofthesCMOSsensorinZylaeliminatestheneedtochoosebetweenlownoise
orhighcapacity,inthatsignalcanbesampledsimultaneouslybybothhighgainandlowgainampliers.As
such,thelowestnoiseofthesensorcanbeharnessedalongsidethemaximumwelldepth,aordingthewidest
possibledynamicrange.Traditionally,scienticsensorsincludingCCD,EMCCD,ICCDandCMOS,demandthat
theusermustselect‘upfront’betweenhighorlowampliergain(i.e.sensitivity)settings,dependingonwhether
they want to optimise for low noise or maximum well depth. Since the true dynamic range of a sensor is
determinedbytheratioofwelldepthdividedbythenoiseoordetectionlimit,thenchoosingeitherhighorlow
gainsettingswillrestrictdynamicrangebylimitingtheeectivewelldepthornoiseoor,respectively.
Forexample,consideralargepixelCCD,with16-bitAnalogtoDigitalConverter(ADC),oeringafullwelldepth
of150,000e-andlowestreadnoiseoorof3e-.Thegainsensitivityrequiredtogivelowestnoiseis1e-/
ADU (or ‘count’) and the gain sensitivity required to harness the full well depth is 2.3 e-/ADU, but with a higher
read noise of 5 e-. Therefore, it does not automatically follow that the available dynamic range of this sensor
is given by 150,000/3 = 50,000:1. This is because the high sensitivity gain of 1e-/ADU that is used to reach 3
e- noise means that the 16-bit ADC will top out at 65,536 e-, well short of the 150,000 e- available from the
pixel. Therefore, the actual dynamic range available in ‘low noise mode’ is 65,536/3 = 21,843:1. Conversely,
thelowersensitivitygainsettingmeansthattheADCwilltopoutat~150,000e-,butthehigherreadnoiseof
5 e- will still limit the dynamic range to 150,000/5 = 30,000:1 in this ‘high well depth mode’. The sCMOS sensor
oersauniquedualamplierarchitecture,meaningthatsignalfromeachpixelcanbesampledsimultaneously
bybothhighandlowgainampliers.Thesensoralsofeaturesasplitreadoutschemeinwhichthetop
and bottom halves of the sensor are read out independently. Each column within each half of the sensor is
equippedwithdualcolumnlevelampliersanddualanalog-to-digitalconverters,representedbytheblock
diagram below:
Figure 12: AmpliersandADCofthesCMOSSensor
Thedualcolumnlevelamplier/ADCpairshaveindependentgainsettings,andthenalimage(seeFigure 13)
is reconstructed by combining pixel readings from both the high gain and low gain readout channels to achieve
awideintra-scenedynamicrange,uniquelysoconsideringtherelativelysmall6.5μmpixelpitch.
Common
Ramp
Signal
Common
Calibration
Signal
Common
Counter
Input
Low Noise
Dual Column
Level Ampliers
Dual Single
Slope 11-bit
ADC
22-bit
Output
Digital
Memory
Digital
Memory
Low
Gain
High
Gain
Analog
Memory
Analog
Memory
+
-
+
-
11
11
11
11
11
Column
Bit Line