3 Operation
(continued)
3-130 C232-302-401/402/403/404-603 / C232/EN M/A23
The output signal of one equation can be processed as the input signal for another
higher-order equation, and this makes it possible to have a sequence of interlinked
Boolean equations. The equations are processed in the sequence defined by the order
of each equation so that the end result of a sequence of interlinked Boolean equations is
given by the highest-order equation.
The output signal of each equation is fed to a separate timer stage that has two timer
elements and a choice of operating modes. This offers the possibility of assigning a
freely configurable time characteristic to the output signal of each Boolean equation. In
the Minimum time operating mode, the setting of timer stage t2 has no effect. Figures
3-99 to 3-103 show the time characteristics for the various timer stage operating modes.
Note: If the unit is set to “off-line“, the equations are not processed and all outputs are
set to a logic value of '0'.
3-99 Operating mode 1: Operate/release delay
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