EasyManua.ls Logo

Astronics OmniBusII - Core Discrete Input;Output (I;O)

Astronics OmniBusII
58 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
OMNIBUS II FEATURES
There are a number of formats for IRIG timing. The OmniBus II family uses the
IRIG formats indicated in Table 4.1. The characteristics of the external electrical
interface to the IRIG pins are as shown in Table 4.2 and Table 4.3.
Format
A
1000 pps
B
100 pps
Modulation Frequency
0 1 Pulse width coded Amplitude modulated
Frequency/Resolution
0
2
3
No carrier/index count interval
1 kHz/1 ms (B only)
10 kHz/.1 ms (A only)
Coded Expressions
0, 1, 2, 3, 4,
5, 6, 7
BCD
TOY
and BCD
YEAR
fields are supported
System Timestamp only reflects BCD
TOY
CF can be set to or read from a register
SBS are ignored on input and 0 on output
Table 4.1—Input and Output IRIG formats
AM IRIG Input Characteristics
Min input impedance (at 1kHz)
10
Max input amplitude (V
pk-pk
)
8V
AM IRIG Output Characteristics
Output mark amplitude (V
pk-pk
)
2.5V to 3.5V
Output space amplitude (V
pk-pk
)
0.75V to 1.25V
Max output resistive load
45Ω
Table 4.2—Electrical characteristics of the AM IRIG signals
Input impedance (min)
12 kΩ
Input voltage (max)
-7.5V to 12.5V volts
Input level threshold
API Controlled (0V-5V)
Output level
0 to 5 volts
Output drive capability
20 mA
Table 4.3—Electrical characteristics of the PCM IRIG signals
The following table lists the protocols supported on each pin. For information on
configuring and using the IRIG timer consult the BTIDriver API programming
manuals.
Note: The timing pins on the OmniBus II family are distinct and
not internally connected as they were in the OmniBus family.
Timing Protocol
Core/Pin
PPS
Core A Pin 17
PCM IRIG
Core A Pin 17
AM IRIG
Core B Pin 17
Table 4.4—IRIG pinout
4.4 Core Discretes
OmniBus products have both input and output discrete capability. OmniBus II
has eight bidirectional TTL level discretes per core which can be used as either
inputs or outputs. All OmniBus II core discrete inputs and outputs are TTL level.
Each discrete output line has a 5-volt TTL driver which can source or sink up to
8 mA and has an individual tristate control; the discrete input receiver is a 5-volt
tolerant device with high input impedance (10µA leakage current). When used as
OmniBus II PCIe/PXIe User’s Manual 4-3

Table of Contents