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Astronics OmniBusII - APPENDIX B REVISION HISTORY
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A
PPENDIX B
REVISION HI
ST
OR
Y
The following rev
isions hav
e been made to this m
anual:
Rev. A
Date:
March
27
, 2014
Initial release of th
is manual.
Rev. B0
Date:
Februrary
6
, 2015
Added updates for Om
ni
Bus II PXI
e
OmniBus II PCIe/PXIe User’s Manual
B-1
56
58
Table of Contents
Main Page
Default Chapter
5
Table of Contents
5
1 Introduction
9
Omnibus II Overview
9
Figure 1.1-Omnibus II Pcie Card
9
Figure 1.2-Omnibus II Pxie Card
10
Omnibus II Configurations
11
Figure 1.3-The Two-Core Architecture of Omnibus II Pcie/Pxie Card
11
Avionics Databus Protocols
12
Other Documentation
12
Support and Service
13
Updates
13
2 Installation
15
Step 1: Insert the Card into the System
15
Step 2: Install the Driver Software
16
Figure 2.1-Pxie Compatible Chassis Glyphs
16
Step 3: Set the Card Number and Test the Installation
17
Step 4: Connect to Databus(S) I/O
17
3 Operation
19
Copilot
19
Figure 3.1-Sample Copilot Screen
19
User-Developed Software
20
4 Omnibus II Features
21
PCI Express Bus
21
Built-In Test
21
IRIG Timer
22
Figure 4.1-Built-In Test and System Monitor Architecture
22
Core Discretes
23
Table 4.1-Input and Output IRIG Formats
23
Table 4.2-Electrical Characteristics of the am IRIG Signals
23
Table 4.3-Electrical Characteristics of the PCM IRIG Signals
23
Table 4.4-IRIG Pinout
23
Avionics Discretes
24
Table 4.5-Hardware Versus Software Designation of Core Discretes
24
Figure 4.2-Omnibus II Discrete Shunt Input Circuit
25
Shunt Input Considerations
25
Shunt Inputs
25
Shunt Outputs
25
Figure 4.3-Omnibus II Discrete Shunt Output Circuit
26
Shunt Output Considerations
26
Shunt Discrete Input/Output Usage
27
Table 4.6-Avionics Discrete I/O Designations
27
5 Omnibus II Pxie Specific Features
29
Clock Switch (CLK SEL)
29
Figure 5.1-Pxie On-Board Clock Switch
29
Pxie Trigger Access
30
Protocol Sync and Trigger Support
30
Table 5.1-Pxie Trigger Signals
30
Table 5.2-Pxie Trigger to Protocol Trigger Mapping
31
Table 5.3-Pxie Trigger to Protocol Sync Mapping
31
Pxie Status
32
Table 5.4-Transitional Protocol Trigger Parameters
32
Table 5.5-Pxie Status Parameters
32
Chassis Slot Glyph
33
Figure 5.2-Pxie Chassis Slot Glyphs
33
6 Module Configurations
35
Omnibus II Pcie Boards
35
Omnibus II Pxie Boards
35
MIL-STD-1553 Modules
35
Table 6.1-Omnibus II Pcie Host Part Numbering
35
Table 6.2-Omnibus II Pxie/Cpcie Host Part Numbering
35
Software-Selectable Bus Termination
36
Table 6.3-MIL-STD-1553 Module Part Numbering
36
Table 6.4-MIL-STD-1553 Level Function Definition
36
Configurable RT Response Time
37
Table 6.5-MIL-STD-1553 Paramamplitudeconfig Configval
37
Table 6.6-MIL-STD-1553 Paramamplitudeconfig Output Drive
37
Variable Transmit Amplitude
37
Zero Crossing Distortion
37
ARINC 429 Modules
38
Table 6.7-ARINC 429 Module New Applications Part Numbering
38
Table 6.8-ARINC 429 Module Deprecated Part Numbering
38
Configurable Frequency
39
Output State
39
Parametric Waveform
39
Table 6.9-ARINC 429 Parametric Waveform Characteristics
39
ARINC 708 Modules
40
Software-Selectable Bus Termination
40
Variable Bit Length
40
Variable Transmit Amplitude
40
Table 6.10-MIL-STD-1553 Module Part Numbering
40
ARINC 717 Modules
41
Variable Transmit Amplitude
41
Table 6.11-ARINC 708 Paramamplitudeconfig Configval
41
Table 6.12-ARINC 717 Module New Applications Part Numbering
41
Table 6.13-ARINC 717 Module Deprecated Part Numbering
41
7 Connector Pinouts
43
Interface Connector
43
General Pinout
43
Module-Specific Wiring
44
Table 7.1-General Pin Designations
44
Mil-Std-1553
45
Table 7.2-Pinouts for MIL-STD-1553 Modules
45
Arinc 429
46
Arinc 708
46
Table 7.3-Pinouts for ARINC 429 Modules
46
Table 7.4-Pinouts for ARINC 708 Modules
47
Arinc 717
48
Standard Cables
49
PN 16035 Cable Assembly: LFH to LFH
49
PN 16036 Cable Assembly: LFH to Two 25-Pin D-Subs
49
Table 7.6-Wiring Chart for 16036 Cable Assembly
50
MIL-STD-1553 Cable Assemblies
51
Table 7.7-MIL-STD-1553 Cable Assembly Configurations
51
Table 7.8-Twinax Wiring on MIL-STD-1553 Cable Assemblies
51
Table 7.9-D-Sub Connector Pinout for Cable Assemblies 16037 and 16039
52
Appendix Acoupling and Termination
53
Bus Termination
53
Transformer Versus Direct Coupling
53
Figure A.1-Transformer Coupling to a Dual-Redundant Databus
54
Figure A.2-Direct Connection to a Dual-Redundant Databus
55
Appendix Brevision History
57
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