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Figure 13-1. 16-bit Timer/Counter Block Diagram
(1)
Note: 1. Refer to Figure 1-2 on page 5 or Figure 1-3 on page 6, Table 9-6 on page 76, and Table 9-15
on page 83 for Timer/Counter
1 and 3 pin placement and description.
13.2.1 Registers
The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register
(ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit
registers. These procedures are described in the section “Accessing 16-bit Registers” on page
116. The Timer/Counter Control Registers (TCCRnx) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible
in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
ICFn (Int.Req.)
TOVn
(Int.Req.)
Clock Select
Timer/Counter
DATABUS
OCRnA
OCRnB
OCRnC
ICRn
=
=
=
TCNTn
Waveform
Generation
Waveform
Generation
Waveform
Generation
OCnA
OCnB
OCnC
Noise
Canceler
ICPn
=
Fixed
TOP
Values
Edge
Detector
Control Logic
=
0
TOP BOTTOM
Count
Clear
Direction
OCFnA
(Int.Req.)
OCFnB
(Int.Req.)
OCFnC
(Int.Req.)
TCCRnA TCCRnB TCCRnC
( From Analog
Comparator Ouput )
Tn
Edge
Detector
( From Prescaler )
clk
Tn
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