62
7679H–CAN–08/08
AT90CAN32/64/128
0x0012 jmp TIM2_COMP ; Timer2 Compare Handler
0x0014 jmp TIM2_OVF ; Timer2 Overflow Handler
0x0016 jmp TIM1_CAPT ; Timer1 Capture Handler
0x0018 jmp TIM1_COMPA; Timer1 CompareA Handler
0x001A jmp TIM1_COMPB; Timer1 CompareB Handler
0x001C jmp TIM1_OVF ; Timer1 CompareC Handler
0x001E jmp TIM1_OVF ; Timer1 Overflow Handler
0x0020 jmp TIM0_COMP ; Timer0 Compare Handler
0x0022 jmp TIM0_OVF ; Timer0 Overflow Handler
0x0024 jmp CAN_IT ; CAN Handler
0x0026 jmp CTIM_OVF ; CAN Timer Overflow Handler
0x0028 jmp SPI_STC ; SPI Transfer Complete Handler
0x002A jmp USART0_RXC; USART0 RX Complete Handler
0x002C jmp USART0_DRE; USART0,UDR Empty Handler
0x002E jmp USART0_TXC; USART0 TX Complete Handler
0x0030 jmp ANA_COMP ; Analog Comparator Handler
0x0032 jmp ADC ; ADC Conversion Complete Handler
0x0034 jmp EE_RDY ; EEPROM Ready Handler
0x0036 jmp TIM3_CAPT ; Timer3 Capture Handler
0x0038 jmp TIM3_COMPA; Timer3 CompareA Handler
0x003A jmp TIM3_COMPB; Timer3 CompareB Handler
0x003C jmp TIM3_COMPC; Timer3 CompareC Handler
0x003E jmp TIM3_OVF ; Timer3 Overflow Handler
0x0040 jmp USART1_RXC; USART1 RX Complete Handler
0x0042 jmp USART1_DRE; USART1,UDR Empty Handler
0x0044 jmp USART1_TXC; USART1 TX Complete Handler
0x0046 jmp TWI ; TWI Interrupt Handler
0x0048 jmp SPM_RDY ; SPM Ready Handler
;
0x004A RESET: ldi r16, high(RAMEND) ; Main program start
0x004B out SPH,r16 ;Set Stack Pointer to top of RAM
0x004C ldi r16, low(RAMEND)
0x004D out SPL,r16
0x004E sei ; Enable interrupts
0x004F <instr> xxx
... ... ... ...
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and Interrupt Vector Addresses is:
;Address Labels Code Comments
0x0000 RESET: ldi r16,high(RAMEND) ; Main program start
0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM
0x0002 ldi r16,low(RAMEND)
0x0003 out SPL,r16
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