82
7679H–CAN–08/08
AT90CAN32/64/128
Table 9-13 and Table 9-14 relates the alternate functions of Port D to the overriding signals
shown in Figure 9-5 on page 72.
Note: 1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins
PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between
the AIO outputs shown in the port figure and the digital logic of the TWI module.
Table 9-13. Overriding Signals for Alternate Functions PD7..PD4
Signal Name PD7/T0 PD6/T1/RXCAN PD5/XCK1/TXCAN PD4/ICP1
PUOE 0 RXCANEN TXCANEN + 0
PUOV 0 PORTD6 • PUD 00
DDOE 0 RXCANEN TXCANEN 0
DDOV 0 0 1 0
PVOE 0 0 TXCANEN + UMSEL1 0
PVOV 0 0
(XCK1 OUTPUT •
UMSEL1 • TXCANEN) +
(TXCAN • TXCANEN)
0
PTOE 0 0 0 0
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI T0 INPUT T1 INPUT/RXCAN XCK1 INPUT ICP1 INPUT
AIO – – – –
Table 9-14. Overriding Signals for Alternate Functions in PD3..PD0
(1)
Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1 PD1/INT1/SDA PD0/INT0/SCL
PUOE TXEN1 RXEN1 TWEN TWEN
PUOV 0 PORTD2 • PUD
PORTD1 • PUD PORTD0 • PUD
DDOE TXEN1 RXEN1 0 0
DDOV 1 0 0 0
PVOE TXEN1 0 TWEN TWEN
PVOV TXD1 0 SDA_OUT SCL_OUT
PTOE 0 0 0 0
DIEOE INT3 ENABLE INT2 ENABLE INT1 ENABLE INT0 ENABLE
DIEOV INT3 ENABLE INT2 ENABLE INT1 ENABLE INT0 ENABLE
DI INT3 INPUT INT2 INPUT/RXD1 INT1 INPUT INT0 INPUT
AIO – – SDA INPUT SCL INPUT
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