Appendix C
Inst. Execution Times
C--8
Instruction Execution Times
DL105 PLC User Manual, 3rd Edition
Logical (Accumulator) Instructions
DL105
Instruction Legal Data Types Execute Not Execute
AND V:Data Reg.
V:Bit Reg.
63 μs
261 μs
10.4 μs
10.4 μs
ANDD K:Constant
53 μs 8.4 μs
OR V:Data Reg.
V:Bit Reg.
59 μs
257 μs
10.4 μs
10.4 μs
ORD K:Constant
49 μs 8.4 μs
XOR V:Data Reg.
V:Bit Reg.
60 μs
257 μs
10.4 μs
10.4 μs
XORD K:Constant
49 μs 8.4 μs
CMP V:Data Reg.
V:Bit Reg.
59 μs
259 μs
10.4 μs
10.4 μs
CMPD V:Data Reg.
V:Bit Reg.
K:Constant
63 μs
257 μs
54 μs
8.4 μs
8.4 μs
8.4 μs
Math Instructions (Accumulator)
DL105
Instruction Legal Data Types Execute Not Execute
ADD V:Data Reg.
V:Bit Reg.
198 μs
397 μs
10.6 μs
10.6 μs
ADDD V:Data Reg.
V:Bit Reg.
K:Constant
198 μs
397 μs
188 μs
8.4 μs
8.4 μs
8.4 μs
SUB V:Data Reg.
V:Bit Reg.
200 μs
397 μs
10.6 μs
10.6 μs
SUBD V:Data Reg.
V:Bit Reg.
K:Constant
198 μs
392 μs
190 μs
8.4 μs
8.4 μs
8.4 μs
MUL V:Data Reg.
V:Bit Reg.
K:Constant
497 μs
483 μs
487 μs
10.6 μs
10.6 μs
8.4 μs
DIV V:Data Reg.
V:Bit Reg.
K:Constant
909 μs
1108 μs
899 μs
10.6 μs
10.6 μs
8.4 μs
INCB V:Data Reg.
V:Bit Reg.
83 μs
349 μs
10.4 μs
10.4 μs
DECB V:Data Reg.
V:Bit Reg.
82 μs
351 μs
10.4 μs
10.4 μs
Logical
Instructions
Math Instructions