Avnet SMARC MSC SM2S-IMX8MINI User Manual

MSC SM2S-IMX8MINI 30 / 87
User Manual
4.3 PCI Express
The i.MX8M Mini SoC supports PCIe x1 Gen2 lane.*
Table 8: PCIe Signal Description
Signal
Pin Type
Signal Level
Pin on
i.MX8M Mini
Pin name on
i.MX8M Mini
Power
Tolerance
PU/PD
Description
PCIE_A_TX+
PCIE_A_TX-
O
LVDS PCIe
B20
A20
PCIE_TXN_P
PCIE_TXN_N
According to
PCIe spec
PCI Express Differential Transmit Pairs. AC
coupled on module
PCIE_A_RX+
PCIE_A_RX-
I
LVDS PCIe
B19
A19
PCIE_RXN_P
PCIE_RXN_N
According to
PCIe spec
PCI Express Differential Receive Pairs
PCIE_A_REFCK+
PCIE_A_REFCK-
O
LVDS PCIe
B21
A21
PCIE_CLK_N
PCIE_CLK_P
According to
PCIe spec
PCI Express Reference Clock. AC coupled
on module. Clock enabled by default.
PCIE_WAKE#
I
3.3V CMOS
N27
NAND_RE_B
3.3V
PU 10k
PCI Express Wake signal. Asserted by
device when requesting wake up.
(CPU GPIO3_IO15)
PCIE_A_RST#
O PP
3.3V CMOS
K27
NAND_CLE
3.3V
PCI Express Reset output signal.
*
NOTE: In case GBE1 Interface is implemented on the module the PCIe Interface will no longer be available. Pins can be left unconnected
4.4 USB
The USB controller supports USB 2.0.
Depending on the module variant the following USB lane options are available:
• Option 1 with USB 2.0 Hub: USB[0] = USB 2.0 host/device OTG compliant
USB[1:4] = USB 2.0 host
• Option 2 without USB 2.0 Hub: USB[0] = USB 2.0 host/device OTG compliant
USB[1] = USB 2.0 host.

Avnet SMARC MSC SM2S-IMX8MINI Specifications

General

Brand	Avnet
Model	SMARC MSC SM2S-IMX8MINI
Category	Control Unit
Language	English