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MSC SM2S-IMX8MINI 33 / 87

User Manual

Signal

Type

Signal Level

Pin on

i.MX8M Mini

Pin name on

i.MX8M Mini

Power

Tolerance

PU/PD

Description

CSI0_CK+

CSI0_CK-

1.8V CMOS

A22

B22

MIPI_CSI_CLK_N

MIPI_CSI_CLK_P

1.8V

CSI differential clock inputs

CSI1_CK+

CSI1_CK-

1.8V CMOS

A19

B19

MIPI_CSI_CLK_N

MIPI_CSI_CLK_P

1.8V

CSI differential clock inputs

CAM_MCK

O PP

1.8V CMOS

J26

CLKOUT2

1.8V

Master clock for camera

I2C_CAM0_CK

O OD

1.8V CMOS

F15

UART2_RXD

1.8V

PU 2.2k 1.8V

CAM0 DDC clock line (CPU GPIO5_IO24)

I2C_CAM0_DAT

I/O OD

1.8V CMOS

E15

UART2_TXD

1.8V

PU 2.2k 1.8V

CAM0 DDC data line (CPU GPIO5_IO25)

I2C_CAM1_CK

O OD

1.8V CMOS

F15

UART2_RXD

1.8V

PU 2.2k 1.8V

CAM0 DDC clock line (CPU GPIO5_IO24)

I2C_CAM1_DAT

I/O OD

1.8V CMOS

E15

UART2_TXD

1.8V

PU 2.2k 1.8V

CAM1 DDC data line (CPU GPIO5_IO25)

CAM0_PWR#

I/O OD

1.8V CMOS

AG14

GPIO1_IO00

1.8V

PU 470k 1.8V

CAM0 Power Enable, active low.

GPIO0 alternate use

CAM1_PWR#

I/O OD

1.8V CMOS

AF14

GPIO1_IO01

1.8V

PU 470k 1.8V

CAM1 Power Enable, active low.

GPIO1 alternate use

CAM0_RST#

I/O OD

1.8V CMOS

AF13

GPIO1_IO03

1.8V

PU 470k 1.8V

CAM0 Reset, active low.

GPIO2 alternate use

CAM1_RST#

I/O OD

1.8V CMOS

AF12

GPIO1_IO05

1.8V

PU 470k 1.8V

CAM1 Reset, active low.

GPIO3 alternate use

NOTE: CSI0 and CSI1 share the same I²C bus.

CAM0 and CAM1 I²C drivers are implemented using bit-banged IO operation.

4.6 LVDS

LVDS channel 0 and 1 are available on the SMARC™ module depending on module variant. An on-module DSI bridge converts the MIPI DSI data

stream to Single-Link LVDS and Dual-link LVDS.

Brand	Avnet
Model	SMARC MSC SM2S-IMX8MINI
Category	Control Unit
Language	English

Avnet SMARC MSC SM2S-IMX8MINI User Manual

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