Avnet SMARC MSC SM2S-IMX8MINI User Manual

MSC SM2S-IMX8MINI 35 / 87
User Manual
Signal
Pin
Type
Signal
Level
Pin on
i.MX8M
Mini
Pin name on
i.MX8M Mini
Power
Tolerance
PU/PD
Description
LVDS1_CK+ / DSI1_CLK+
LVDS1_CK- / DSI1_CLK+
O
LVDS
n.a.
n.a.
2.8V
LVDS Channel 1 differential clock
LCD0_VDD_EN
O PP
1.8V
CMOS
AF21
SAI1_TXD3
1.8V
PD 10k
LCD0 panel power enable (CPU
GPIO4_IO15)
LCD0_BKLT_EN
O PP
1.8V
CMOS
AF20
SAI1_TXD1
1.8V
LCD0 backlight enable (CPU GPIO4_IO13)
LCD0_BKLT_PWM
O PP
1.8V
CMOS
AF8
SPDIF_EXT_CLK
1.8V
PD 10k
LCD0 backlight brightness control
(PWM1_OUT)
LCD1_VDD_EN
O PP
1.8V
CMOS
AG22
SAI1_TXD4
1.8V
PD 10k
LCD1 panel power enable (CPU
GPIO4_IO16)*
LCD1_BKLT_EN
O PP
1.8V
CMOS
AG21
SAI1_TXD2
1.8V
LCD1 backlight enable (CPU GPIO4_IO14)*
LCD1_BKLT_PWM
O PP
1.8V
CMOS
AG9
SPDIF_RX
1.8V
PD 10k
LCD1 backlight brightness control
(PWM2_OUT)*
I2C_LCD_CK
O PP
1.8V
CMOS
D13
I2C4_SCL
1.8V
PU 2.2k
1.8V
I²C clock output for LVDS display use
I2C_LCD_DAT
I/O OD
1.8V
CMOS
E13
I2C4_SDA
1.8V
PU 2.2k
1.8V
I²C data line for LVDS display use
*
NOTE: LCD1_VDD_EN, LCD1_BKLT_EN and LCD1_BKLT_PWM can be left unconnected in case dual-link LVDS is used
The DSI-LVDS Bridge is only capable of a single-link output on channel 0 or a dual-link output on channel 0 and 1. A simultaneous output of the same source on LVDS
channel 0 and channel 1 or independent usage on LVDS channel 0 and channel 1 is not supported.
4.7 SPI Bus
The i.MX8M Mini SMARC module offers two Enhanced Configurable SPI (ECSPI) busses with two slave select signals each.
Key features of the ECSPI include:
• Full-duplex synchronous serial interface

Avnet SMARC MSC SM2S-IMX8MINI Specifications

General

Brand	Avnet
Model	SMARC MSC SM2S-IMX8MINI
Category	Control Unit
Language	English