Avnet SMARC MSC SM2S-IMX8MINI User Manual

MSC SM2S-IMX8MINI 57 / 87
User Manual
6.2 SPI Devices
Table 25: SPI Interfaces Overview
CPU Interface
Chip Select
CPU Pin
CPU Pin Name
Device
SMARC Connector
Description
ECSPI1
CS0
B6
ECSPI1_SS0
SPI0_CS0#
CS1
AD22
SAI2_TXC
SPI0_CS1#
GPIO based chip select
(CPU GPIO4_IO25)*
CS1
AD22
SAI2_TXC
CAN0 Controller
Dedicated chip select for
CAN0 Controller*
ECSPI2
CS0
A6
ECSPI1_SS0
SPI1_CS0#
CS1
AC22
SAI2_TXD0
SPI1_CS1#
GPIO based chip select
(CPU GPIO4_IO26)*
CS1
AC22
SAI2_TXD0
CAN1 Controller
Dedicated chip select for
CAN1 Controller*
QSPI_A
CS0
N24
NAND_CE0_B
QSPI NOR Flash
Dedicated chip select for
QSPI NOR Flash*
*
NOTE: SPI[0:1]_CS1# are not available if the CAN interfaces are implemented on the module.
The on-module QSPI NOR Flash is an assembly option.

Avnet SMARC MSC SM2S-IMX8MINI Specifications

General

Brand	Avnet
Model	SMARC MSC SM2S-IMX8MINI
Category	Control Unit
Language	English