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Avnet SMARC MSC SM2S-IMX8MINI User Manual

Avnet SMARC MSC SM2S-IMX8MINI
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User Manual
5.2.2 Reset Sequencing
I.MX8M Mini can’t be reset by internal reset and a power cycle is preferred. Some peripherals require a power cycle during system reset.
RESET_IN# assertion leads to a module power cycle as shown in the following figure:
Figure 5-3: Reset Sequencing
Figure 5-4: Reset Timings
Time Slot
Description
Value
T1
CARRIER_PWR_ON to RESET_IN# timing
10.8ms
T2
RESET_OUT# to CARRIER_PWR_ON
355ms
RESET_IN# (Carrier to Module)
CARRIER_PWR_ON (Module to Carrier)
CARRIER_STBY# (Module to Carrier)
RESET_OUT# (Module to Carrier)
T1
T2
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Avnet SMARC MSC SM2S-IMX8MINI Specifications

General IconGeneral
ProcessorNXP i.MX 8M Mini
CPU SpeedUp to 1.8 GHz
GPUGC7000Lite
RAMUp to 4 GB LPDDR4
ConnectivityWi-Fi, Bluetooth
EthernetGigabit Ethernet
USBUSB 2.0, USB 3.0
Operating SystemLinux, Android
Operating Temperature-40°C to +85°C
Form FactorSMARC 2.0
CPU ArchitectureARM Cortex-A53
StorageeMMC, SD card
Display InterfaceHDMI, MIPI DSI
Camera InterfaceMIPI CSI

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