Avnet SMARC MSC SM2S-IMX8MINI - Page 36

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User Manual
• Master/Slave configurable
• Two Chip Select (CS) signals to support multiple peripherals
• Transfer continuation function allows unlimited length data transfers
• 32-bit wide by 64-entry FIFO for both transmit and receive data
• Polarity and phase of the Chip Select (CS) and SPI Clock (SCLK) are configurable
• Direct Memory Access (DMA) support
Table 12: SPI Signal Description
Signal
Pin
Type
Signal Level
Pin on
i.MX8M Mini
Pin name on
i.MX8M Mini
Power
Tolerance
PU/PD
Description
SPI0_DIN
I
1.8V CMOS
A7
ECSPI1_MISO
1.8V
Master Input Slave Output
SPI0_DO
O PP
1.8V CMOS
B7
ECSPI1_MOSI
1.8V
Master Output Slave Input
SPI0_CK
O PP
1.8V CMOS
D6
ECSPI1_SCLK
1.8V
Clock Output
SPI0_CS0#
O PP
1.8V CMOS
B6
ECSPI1_SS0
1.8V
PU 10k 1.8V
Chip-Select 0
SPI0_CS1#
O PP
1.8V CMOS
AD22
SAI2_TXC
1.8V
PU 10k 1.8V
Chip-Select 1 (GPIO4_IO25)
*
SPI1_DIN
I
1.8V CMOS
A8
ECSPI2_MISO
1.8V
Master Input Slave Output
SPI1_DO
O PP
1.8V CMOS
B8
ECSPI2_MOSI
1.8V
Master Output Slave Input
SPI1_CK
O PP
1.8V CMOS
E6
ECSPI2_SCLK
1.8V
Clock Output
SPI1_CS0#
O PP
1.8V CMOS
A6
ECSPI2_SS0
1.8V
PU 10k 1.8V
Chip-Select 0
SPI1_CS1#
O PP
1.8V CMOS
AC22
SAI2_TXD0
1.8V
PU 10k 1.8V
Chip-Select 1 (GPIO4_IO26)
*
*
NOTE: SPI[0:1] are not available if CAN[0:1] interfaces are implemented on the module.