MSC SM2S-IMX8MINI 42 / 87
User Manual
The I²C bus driven by CPU core function has the following key features:
• Compatible with I2C bus standard
• Multimaster operation
• Software programmability for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated Start signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
• Data rates up to 100kbits/s in Standard mode and 400kbits/s in Fast mode
Table 17: I²C Signal Description
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