Avnet SMARC MSC SM2S-IMX8MINI User Manual

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User Manual
The I²C bus driven by CPU core function has the following key features:
• Compatible with I2C bus standard
• Multimaster operation
• Software programmability for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated Start signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
• Data rates up to 100kbits/s in Standard mode and 400kbits/s in Fast mode
Table 17: I²C Signal Description
Signal
Pin
Type
Signal Level
Pin on
i.MX8M Mini
Pin name on
i.MX8M Mini
Power
Tolerance
PU/PD
Description
I2C_GP_CK
O OD
1.8V CMOS
E10
I2C2_SCL
1.8V
PU 2.2k 1.8V
General Purpose SMB clock output
I2C_GP_DAT
I/O OD
1.8V CMOS
F10
I2C2_SDA
1.8V
PU 2.2k 1.8V
General Purpose SMB data I/O line
SMB_ALERT_1V8#
I OD
1.8V CMOS
AF9
SPDIF_TX
1.8V
PU 2.2k 1.8V
Interrupt Signal (GPIO5_IO03)

Avnet SMARC MSC SM2S-IMX8MINI Specifications

General

Brand	Avnet
Model	SMARC MSC SM2S-IMX8MINI
Category	Control Unit
Language	English