3.2.2 Reducing the Sampling Frequency
It could be required to operate the DT5740 at a sampling frequency (SAMP-CLK) lower than the
nominal. In principle, this can be alternatively achieved by:
1. Direct way: reprogramming the AD9520 dividers. REF-CLK can be configured as in § 3.2.1. Not
all the frequencies are admitted and a lower frequency limit must be considered, due to the
internal electronics.
NOTE: please, contact CAEN (§ 8) for the feasibility of this method and to receive the PLL
programming file.
2. Indirect way: enabling the Decimation option in the firmware (see § 3.2.3).
3.2.3 Decimation
This functionality is a firmware option based on the programmability of a decimation factor n.
During the acquisition, the firmware processes the digitized input waveforms calculating an
averaged value of the “decimated” 2
n
consecutive
samples. The self-trigger is then issued as soon
as an averaged value exceeds the programmed threshold (see § 3.4.3). Software trigger and
external trigger are not affected by decimation option.
While the real sampling frequency doesn’t change (i.e. 62.5 MS/s), the decimation effect is to
change the rate the data are written into the digitizer memory. The readout data result so at a
sampling frequency changed according to the formula:
where n = [0,1,…,7].
The n paramenter is set through the register address 0x8044 (see § 1).
Decimation functionality is supported by:
CAENDigitizer library revision ≥ 2.5.0
WaveDump software revision ≥ 3.6.4
NOTE: Decimation is supported only by 740 series running a AMC FPGA firmware revision ≥ 0.7
(see § 7.1.1).
3.2.4 Trigger Clock
The Trigger logic (TRG-CLK) works at 125-MHz frequency (2* SAMP_CLK), while, at the
motherboard level, triggers are sensed, generated and distributed at 62.5-MHz frequency. The
actual trigger clock frequency is so the same as the sampling one (see also § 3.3.2).
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