3.3.4 Event Structure
The event can be readout via Optical Link or USB; data format is 32-bit long word (see Fig. 3.4).
An event is structured in:
Header (four 32-bit words)
Data (variable size and format)
3.3.4.1 Header
The Header consists in 4 words including the following information:
EVENT SIZE (Bit[27:0] of 1
st
header word) = it is the size of the event (number of 32-bit long
words);
BOARD FAIL flag (Bit[26] of 2
nd
header word) = implemented from ROC FPGA firmware
revision 4.5 on (reserved otherwise), this bit is set to “1” in consequence of a hardware
problem (e.g. PLL unlocking). The user can collect more information about the cause by
reading at register address 0x8104 and contact CAEN Support Service if necessary (see § 8);
EVENT MODE (Bit[24] of 2
nd
header word) = this bit identifies the event format; with the
default firmware, it is reserved and must be 0;
TRIGGER OPTIONS (Bit[23:8] of 2
nd
header word) = starting from revision 4.6 of the ROC
FPGA firmware, these 16 bits can be programmed to provide different trigger information
according to the setting of the bits[22:21] at registeraddress 0x811C (Table 3.2);
NOTE: or ROC FPGA firmware revisions lower than 4.6. these bits are reserved.
Table 3.2: Pattern configuration table
Indicates the trigger source causing the
event acquisition:
Bits[23:19] = 00000
Bit[18] = Software Trigger
Bit[17] = External Trigger
Bit[15:12] = 0000
Bits[11:8] = Trigger requests from the
groups (refer to § 3.4.3)
A 48-bit Trigger Time Tag (ETTT)
information is configured, where
Bits[23:8] contributes as the 16 most
significant bits together to the 32-bit
TTT field (4
th
header word)
NOTE: in the ETTT option, the overflow
bit is not provided
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