Canon EOS 50 E - Built-In Flash

2.1 O Built-in Flash
1) Charge Sequence
Part 2: Technical Information
1. The EFIC receives the order to start charging from the MPU, it puts a high on the
OSC line. This starts the Schmitt trigger circuit producing the high voltage.
2. The EFIC monitors the main capacitor voltage through a voltage divider network
on the SENSE line. When charge ready voltage is reached, it informs the MPU.
3. The MPU informs the LCD-DR to light the flash mark on the LCD.
4. When the full charge voltage is reached, the EFIC sends the OSC signal low stop-
ping the charge.
5. The EFIC informs the MPU and the MPU terminates the charge sequence.
2) Flash Firing and Termination Sequence
1. The MPU outputs film speed (ISO) data to OPAMPl on DAI and DA2.
2. The data is converted in OPAMPland sent to the EFIC on DAC 1 and DAC2.
3. The X sync on signal from the shutter is input to EFIC on the SYNC line and out-
put as a low on SPCR.
4. SPCR is input to MD2 on /TIN and output on TOUT to control the VPP level of
IGBT-DR.
5. IGBT-DR amplifies this and outputs it to trigger the IGBT in the built-in flash
with a high.
6. When the IGBT-DR is triggered, the flash fires.
7. EFIC monitors and integrates the flash output. When it reaches the predeter-
mined level input by DAC, it terminates the flash.
8. The process is the reverse of the trigger process and involves the Motor-Driver IC,
IGBT-DR and IGBT going low and stopping the flash.
MD1
VPP 15 i/,
MPU
w
<I)
ffi
<I)
R5s
7.87K
cs,
0.01
D6s
S5688G
DX1
SYNCl-'-
7
--~,,,,,.,_-c,u_,~JC~
44
EFIC
OP AMP•
Fig. 2-31 Built-in Flash
2-39