Clevo NB50TK1 - Ps8330 B

Schematic Diagrams
B - 20 PS8330B
B.Schematic Diagrams
PS8330B
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
DESIGN NOTE:CFG0
Configuration pin for automatic EQ and
Aux interception; Internal pull down at
~150Kohm,3.3V I/O
L: default, automatic EQ enable and Aux interception enable
H: automatic EQ disable and AUX interception enable
M: automatic EQ disable and AUX interception
disable,no pre-emphasis, 600mVpp swing
DESIGN NOTE:CFG1
Configuration pin for auto test and input offset
cancellation,3.3V IO, internal pull up at~150K
H: default, auto test disable and input offset cancellation
enable
L: auto test enable and input offset cancellation enable
M: auto test disable and input offset cancellation disable
DESIGN NOTE:PEQ
Programmalbe input equalization levels;internal pull
down at~150k ,3.3v I/O
L: default, LEQ, compensate channel loss up to 12dB at
HBR2
H: HEQ, compensate channel loss up to 15dB at HBR2
M:LLEQ, compensate channel loss up to 5dB at HBR2
MINI DISPLAY PORT A(PS8330B)
Hybrid DDC/AUX
DDC DATA/CLK
暞ẞ㔠
:41pcs
PDB PIN:
L:Chip power down
H:Normal operation(default)
月
PS8330B
月
Mini DP Conn
PS8330B
ℏ悐㚱㈿
ESD,3/17
Tim
20171121
DEL
20171123
add
3.3VS
3.3VS
3.3VS
3.3VS
3.3VS3.3VS
3.3VS
3.3VS
3.3VS
3.3VS 3.3VS
3.3VS
3.3VS
MDP_E_AUX#_SDA16,21
MDP_E_AUX_SCL16,21
mDPA_0P21
mDPA_2P21
mDPA_1P21
mDPA_1N21
mDPA_3N21
mDPA_0N21
mDPA_2N21
mDPA_3P21
PS8330B_EC2 40
PS8330B_PCH 31
DP_TDB_AUX#_E 21
DP_TDB_AUX_E 21
MDP_E_HPD_R 21
G_MDPE_MODE 21
D_MDP_E0 21
D_MDP_E#0 21
D_MDP_E1 21
D_MDP_E#1 21
D_MDP_E2 21
D_MDP_E#2 21
D_MDP_E3 21
D_MDP_E#3 21
MDP_E_HPD 17,21,28
Title
Size Document Number Rev
Date: Sheet
of
6-71-NB500-D02
D02
[19] PS8330B DP REPEATER (NV)
A3
19 57Friday, December 29, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NB50TJ1-D02
Title
Size Document Number Rev
Date: Sheet
of
6-71-NB500-D02
D02
[19] PS8330B DP REPEATER (NV)
A3
19 57Friday, December 29, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NB50TJ1-D02
Title
Size Document Number Rev
Date: Sheet
of
6-71-NB500-D02
D02
[19] PS8330B DP REPEATER (NV)
A3
19 57Friday, December 29, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NB50TJ1-D02
C568 0.1u_10V_X7R_04
PS8330B
C616 0.1u_10V_X7R_04
PS8330B
R483 *0_04
PS8330B
C566 0.1u_10V_X7R_04
PS8330B
C574 0.1u_10V_X7R_04
PS8330B
C583
0.1u_10V_X7R_04
PS8330B
Q39
MTP3415KN3
PS8330B
G
D S
C549 0.1u_10V_X7R_04
PS8330B
R118
*4.7K_04
PS8330B
C618
2.2u_6.3V_X5R_04
PS8330B
R487 100K_04
PS8330B
R429
*4.7K_04
PS8330B
C585 0.1u_10V_X7R_04
PS8330B
C609
0.01u_16V_X7R_04
PS8330B
C556 0.1u_10V_X7R_04
PS8330B
C617
0.1u_10V_X7R_04
PS8330B
R115 *4.7K_04
PS8330B
PS8330B
U37
PS8330B
PS8330B
VDD33
1
CEXT
2
I2C_ADDR
3
SCL_CTLPEQ
4
SDA_CLTCFG0
5
VDD33
6
REXT
7
CAD_SRC
8
HPD_SRC
9
CAD_SNK
10
HPD_SNK
11
VDD33
12
OUT3n
13
OUT3p
14
NC
15
OUT2n
16
OOUT2p
17
GND
18
OUT1n
19
OUT1p
20
NC
21
OUT0n
22
OUT0p
23
GND
24
VDD33
36
RST#
35
SDA_DDC
34
SCL_DDC
33
VDD33
32
GND
31
AUX_SRCp
30
AUX_SRCn
29
AUX_SNKp
28
AUX_SNKn
27
PD#
26
VDD33
25
IN3n
48
IN3p
47
NC
46
IN2n
45
IN2p
44
NC
43
IN1n
42
IN1p
41
CFG1
40
IN0n
39
IN0p
38
NC
37
EPAD
49
R490
10K_04
PS8330B
R426
4.7K_04
PS8330B
Q37
MTP3415KN3
PS8330B
G
D S
C578 0.1u_10V_X7R_04
PS8330B
C575 2.2u_6.3V_X5R_04
PS8330B
C580 0.1u_10V_X7R_04
PS8330B
C554 0.1u_10V_X7R_04
PS8330B
R488
100K_04
PS8330B
C587 0.1u_10V_X7R_04
PS8330B
C562 0.1u_10V_X7R_04
PS8330B
R428
4.99K_1%_04
PS8330B
R609
*0_04
PS8330B
R486 *0_04
PS8330B
C582 0.1u_10V_X7R_04
PS8330B
R427
*4.7K_04
PS8330B
R438 *4.7K_04
PS8330B
R430
*4.7K_04
PS8330B
C572 0.1u_10V_X7R_04
PS8330B
C560 0.1u_10V_X7R_04
PS8330B
Q33
2SK3018S3
PS8330B
G
DS
C576 0.1u_10V_X7R_04
PS8330B
C551 0.1u_10V_X7R_04
PS8330B
R417
4.7K_04
PS8330B
R434
4.7K_04
PS8330B
PS8330B_CFG0
PS8330B_CFG1
PS8330B_PEQ
PS8330B_AUXn
PS8330B_AUXp
mDPA_AUXN
mDPA_AUXP
IN_CAD_SRC
G_MDPE_MODE
PS8330B_CFG1
PS8330B_CFG0
IN_CAD_SRC
PS8330B_PEQ
MDP_E_HPD_R
mDPA_AUXN mDPA_AUXP
PS8330B_AUXp PS8330B_AUXn
DP_TDB_AUX_E
IN0P_R
IN0N_R
IN1N_R
IN1P_R
IN2N_R
IN2P_R
IN3N_R
IN3P_R
D_MDP_E#0
D_MDP_E0
D_MDP_E#1
D_MDP_E1
D_MDP_E#2
D_MDP_E2
D_MDP_E#3
D_MDP_E3
DP_TDB_AUX#_E
Sheet 19 of 57
PS8330B