ConMed ExcaliburPLUS PC - Controller Hardware and Memory

Capacitors A4C8 and C9 filter the +16 and +8
Vdc sources. The +16 Vdc source supplies
A4VRI, which provides regulated +12 Vdc and
+12 GND to the Power Amplifier gate driver
ICs, A4U1 and U2. Both +16 and +8 Vdc then
feed the rest of the low-voltage dc loads via con-
nector A4J1.
Harness A9W6 carries +16 and +8 Vdc to the
A2 Display and A3 Controller PWBs mounted
inside the shield on the top cover, A8.
3.3 Controller Hardware
The Excalibur Plus PC™ Controller PWB
Assembly is based on the 8031, a single chip, 8-
bit microprocessor which utilizes external pro-
gram memory. Refer to Schematic 4.4a. This
controller has the following features:
1. Four 8-bit Ports (0,1,2,3) which are individual-
ly addressable as 32 Input/Output (I/O) lines.
2. Two 16-bit timer/event counters, one of which
is used as a software controlled tone generator via
the serial transmit pin TXD (U3 Pin 11).
3. 64 K bytes of externally addressable program
memory (A3U1).
4. On-chip oscillator and clock circuit which is
connected to an external 10 MHz clock signal
derived from a 20 MHz quartz time base (A3Y1).
5. 128 bytes of internal RAM used as a “scratch
pad” by the processor.
6. Battery backed static RAM. This is used both
for “scratch pad” RAM, and for storage of cali-
bration values and user stored “Program” settings.
Minimum battery life is 10 years.
The remainder of the controller circuitry consists
of the Watchdog Timer (WDT), Power On Reset
(POR), Address Decoder, Peripheral Interface
Adapter (PIA), Base Voltage Generator (BVG),
Current Sensing Circuit, Waveform Generator
(WEG), Tone Generator, and the Aspen Return
Monitor (A.R.M.) DAC and current source.
3.3.1 Watchdog Timer (WDT)
The function of this circuit is to monitor the
microprocessor for a failure that would cause
unpredictable results. During normal operation,
the microprocessor program executes in a known
sequence. If a software error is detected, an inter-
nal interrupt is generated which halts the opera-
tion of the microprocessor. If there is a hardware
failure sensed by software control, program execu-
tion will again be terminated.
Should a failure occur in the CPU that prevents
the detection of a problem, thus allowing pro-
gram execution in a random manner, the
Excalibur Plus PC™ is designed so that the WDT
detects the problem. The WDT shuts down the
malfunctioning unit to minimize the effects of the
failure. This is accomplished by requiring the
microprocessor to write to the WDT once during
each program execution cycle. This WRITE
PULSE is referred to as the Watchdog Timer
Strobe (WDTSTB). The WDT circuit must hear
from the microprocessor within a hardware set
window. If the WDTSTB occurs early because
the program “skipped” a portion of the software
or late because it was “hung” in a program loop,
the following results:
1. The circuit latches in the failed condition so
that further strobing from the microprocessor
cannot clear the previous failure.
2. An interrupt (/WDTINT) is generated which
stops abnormal program execution. If the micro-
processor can still respond to the interrupt, a
“fatal” software routine will execute, displaying an
error code “Err 4.2”.
3. The interrupt signal /WDTINT, is used to gen-
erate /WDTFL, which disables the Base Voltage
Generator and Waveform Generator, preventing
further generation of RF output.
The Watchdog Timer (WDT) is made up of a
dual, retriggerable, one-shot multivibrator (U7),
associated RC timing components (R4, C5, R6,
and C6), the relay power enable register (U10),
and associated gates (U5 and U6). A WDTSTB
is generated whenever U10-2 and U10-3 are both
low. The first stage one-shot is set to time out at
the minimum WDTSTB interval by the RC com-
bination of R4 and C5. With C5=1yf, the time