ConMed ExcaliburPLUS PC - Page 38

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is equal to R4(K ohms) in milliseconds.
Example: if R4=10K, the time is 10 millisec-
onds. The trailing (falling) edge of WDTSTB
triggers the first stage causing Ol (U7-6) to go
true (high) for the time interval. The rising edge
of Ol triggers the second stage one-shot via U7-
12, causing Q2 (U7-10) to go high and /Q2
(U7-9) to go low. The timing of this stage is set
by the RC combination of R6 and C6. In normal
operation WDT strobes will occur after stage 1
has timed out (Q1=0) but before stage 2 times
out (Q2=1). The one-shot is retriggerable and
the rising edge of O1 will restart the timing
seguence in the second stage even though it may
not have completed its current time delay.
Normal operation is indicated by /WDTINT
(Q2) never going low.
The relay enable flag, RLYEN-Q from U10-10, is
reset on power-up. This permits the microproces-
sor (U3) to test the WDT during initialization
without allowing RF to appear at the outputs.
While RLYEN-Q is disabled (low), the WDT will
not lock up, permitting the software to test for
correct operation. This is done by strobing the
WDT early, late and looking for the generation of
the interrupt /WDTINT (02-0). The WDT is
then triggered within the correct time window
and should result in /WDTINT remaining high.
If these results are obtained, the WDT timer cir-
cuitry is operating normally.
After initialization is complete, the microproces-
sor generates a WDTSTB at the start of the first
normal program timing cycle. The relay enable
flag, RLYEN-Q, is set by the NOR gate, U10-5
and U10-6 both going low. After this, the pro-
gram enters the normal operation program loop.
Ifa WDTSTB is not generated within the period
of the previous strobe, the second stage will time
out and Q2 will go low resulting in a /WDTINT.
Since RLYEN-Q and /Q2 (U7-9) are high, the
inputs to U6-4 and U6-5 are both true resulting
in its output (U6-6) going low. This resets the
first stage one-shot. Now that Ol (U7-6) cannot
go high, Q2 (U7-12) is prevented from being
retriggered. With the WDT Q2 output gone low,
the microprocessor will execute a WDT failure
interrupt routine in response to /WDTINT
falling, and /WDTEL will disable drive to the
power amplifier.
If the WDTSTB is generated carly, while O1 is
high, the NAND gate (U6-1 and U6-2) will both
be high resulting in U6-3 going low and resetting
the second stage. This causes the same results as
the late strobe described above.
Note that the signal which causes the WDT to
latch and ignore all subsequent WDTSTB pulses
is RLYEN-Q being high. The only way to reset
RLYEN-Q is a Power On Reset.
3.3.2 Power On Reset
The
Power On Reset (POR) circuit consists of a
single chip specifically designed for this function,
A3U4, and associated components R1 and US.
The POR circuit monitors +5 Vdc (U4-8) and
the output signals RST (pin 5) and /RST (pin 6)
become active if +5 Vdc falls below 4.75 Vdc.
The 8031 microprocessor operation is specified
down to 4.5 Vdc. This allows power supply mar-
gin for proper power down of the controller until
reset occurs. When /RST is low, the microproces-
sor is reset via the Inverter U5-12. This prevents
inadvertent writes to the NOVRAM during
power transitions, when the control and
address/data busses are in unknown conditions.
On power up, RST and /RST are kept active for
a minimum of 250 msec to allow the power sup-
ply and microprocessor to stabilize.
The power monitor (U4), also provides an input
(pin 1) for direct connection to a switch (A3S1-
4). Anytime /PB is low for over 10 msec, the
outputs RST and /RST become active. They
remain active for a minimum of 250 msec after
the switch is moved from the “/RST” position.
One last feature of this circuit is its function as a
secondary watchdog timer. This is enabled by the
connection of Address Latch Enable (ALE) from
the microprocessor (U3-30) to U4-7. The RST
and /RST outputs are forced to an active state
when the /ST input (U4-7) is not stimulated for
1.2
seconds. This function is not normally used
because it requires a failure in the microprocessor
and the Watchdog Timer circuitry. This is consid-
ered a double fault condition and the odds of the
two occurring simultaneously are very low. Also,
it is possible for ALE to continue in normal oper-
ation while other parts of the microprocessor are
not. The WDT circuit described previously, is