ConMed ExcaliburPLUS PC - Signal Generation and Monitoring Circuits

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code used in calibration) is located in the odd 4K
blocks. The gate function at U8 thus ensures that
calibration code cannot be accessed when in the
run mode.
The address latch at U24 captures the low order
address byte (AO - A7) when control line ALE is
active. The data is then enabled on to the same
bus when /PSEN and ALE are both low (0,0).
In this manner the address/data bus (ADO -
AD7), alternates between carrying the low order
address for the next instruction from the micro-
processor and reading the data, which is the code
for the next program step, back to the micro-
processor. The high order address bus (A8 -
A14), is used for addresses only and does not
require latching since the information is available
during the entire memory read operation. The
only time /PSEN is active is during a program
instruction fetch. When the microprocessor is
addressing external I/O, such as the PIA or
NOVRAM, the signal/PSEN remains high. ADO-
AD7 is an I/O bus whenever /PSEN is high.
The Nonvolatile Random Access Memory
(NOVRAM), U2, is a battery backed static RAM.
This device stores the calibration coefficients,
power settings and user programs used by the
microprocessor to control accurate power output
levels and to measure return electrode resistance.
When the ESU is powered up, the data stored is
accessed by the microprocessor via the
address/data bus.
3.3.5 Base Voltage Generator
The base voltage generator is schematically
depicted on the A3 Controller Board Schematic
4.40. It is microprocessor controlled with two
analog feedback paths that can turn the base volt-
age down in case of excessive power amplifier
current and high output voltage. The high volt-
age shutback is not active in monopolar coag
modes.
The base voltage generator is made up of an 8 bit
DAC (U20), a differential amplifier (1/4 of U21),
an inverting breakpoint summing amplifier (1/4
of U21), and power transistor A8Q1. U20 pro-
vides the input voltage selected by the micro-
processor by the address lines ADO-AD7. R25 is
a passive pulldown required by the DAC to reach
the lower DAC output voltages. Since resistor
3-6
R32 includes the power transistor A8Q] in the
opamp feedback loop, the combination of Q1
and U21 (pins 1, 2, and 3) may be considered as
a power opamp for analysis purposes.
The -ISENSE and IGND signals are developed in
the RF power amplifier on the Power Conversion
Board A4. These signals are generated by the
power amplifier supply current passing through
sense resistor A4R8. The resulting voltage -
ISENSE is proportional to the total de current
used by the RF power amplifier. The portion of
U21 that includes pins 5,6, and 7 makes up a low
pass filtered differential voltage amplifier that
amplifies the -ISENSE voltage by 10. The result-
ing ISENSE voltage is proportional to the de cur-
rent drawn by the Excalibur Plus PC™ RF power
amplifier from the +110V supply. When
ISENSE exceeds the voltage at U21-3 by a diode
voltage drop, the ISENSE feedback loop becomes
dominant and backs VBASE down to maintain
the RF power amplifier current at its limit. This
is independent of microprocessor control and is
an additional safety feature.
When the Excalibur Plus PC™ is in a monopolar
coag mode, either WV6, WV7, or both will be
high, thus forcing pin U8-6 high, which in turn
makes U12-12 go low. This action prevents the
VSENSE voltage from turning back VBASE to
limit RF output voltage. In all other modes,
U12-12 floats and allows VSENSE to be active.
When VSENSE exceeds the voltage at U21-3 by
a diode voltage drop, the VSENSE feedback loop
becomes dominant and turns VBASE down to
limit the amount of RF output voltage. This
action occurs primarily at high power settings of
monopolar cut and blend modes at high load
impedances to prevent excessive arcing at the
active electrode.
The foregoing action takes place only in Spray
Coag. In Standard Coag, VSENSE feedback gain
is present but highly attenuated by R43 in order
to limit RF leakage.
The inverting breakpoint amplifier (pins 1, 2, and
3 of U21) gain varies with the VDAC input volt-
age. Refer to Fig. 3.1. When VDAC is in the
high range (producing a low VBASE since the
amplifier inverts), the incremental gain is -
R32/R26. This low gain provides a finer control
of VBASE at the low power settings. At lower
VDAC voltages, diode D5 becomes forward