7. BIOS Setup
PC-686BX(NLX)-LV, PC-686BX(NLX)-LVV
89
POST Codes
Table 7.4. POST Codes < 1 / 5 >
CFh Test CMOS R/W function.
C0h
Initialize initial chipset:
Disable shadow RAM.
Disable L2 cache (Socket7 and above).
Set base chipset register.
C1h
Detect memory:
Automatically detect DRAM size, type and ECC.
Automatically detect L2 cache (Socket7 and above).
C3h Expand compressed BIOS code in DRAM.
C5h Call chipset hook and copyback BIOS to E000 & F000 shadow RAM.
01h Extend Xgroup code located at physical address 1000:0.
02h Not used
03h Initial super I/O_Early_Init switch
04h Not used
05h
1. Clear screen.
2. Clear CMOS error flag.
06h Not used
07h
1. Clear 8042 interface.
2. Initialize 82.042 self-test.
08h
1. Test special keyboard controller on Winbond 977 series super I/O chip.
2. Enable keyboard interface.
09h Not used
0Ah
1. Disable PS/2 mouse interface. (option)
2. Automatically detect keyboard and mouse ports then swap ports and interfaces. (option)
3. Reset keyboard on Winbond 977 series super I/O chip.
0Bh Not used
0Ch Not used
0Dh Not used
0Eh
Test F000h segment shadow to verify reading and writing OK. If test fails, sound alarm tone
from speaker.
0Fh Not used
10h
Automatically detect flash type and load the flash R/W code to the F000 runtime area that
supports ESCD and DMI.
11h Not used
12h
Use the walking 1 algorithm to test the CMOS circuit interface. Set realtime clock power supply
status and verify overwrite.
13h Not used
14h
Set default values to chipset. The chipset default values can be changed to MODBIN form by
OEM customer.
15h Not used
16h Initial_Init_Onboard_Generator switch
17h Not used
18h Detect CPU data including brand, SMI type (Cyrix or Intel), CPU level (586 or 686).
POST (hex) Description
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