5. CPU Board Resources
36
PC-686BX(NLX)-LV, PC-686BX(NLX)-LVV
PCI Interrupt Routing Map
This section describes interrupt sharing and how interrupt signals are connected
between the PCI expansion slots and on-board PCI devices. The PCI specification
stipulates how interrupts are shared between devices connected to the PCI bus. In
most cases, the additional delay time caused by sharing an interrupt does not affect
device operation or throughput. However, in some special cases when maximum
performance is required from a device, the device cannot share an interrupt with other
PCI devices. To avoid interrupt sharing with PCI add-in boards, you need to take
note of the following points.
PCI devices are divided into the following categories to determine their interrupt
group.
- INTA:
By default, all add-in boards that require a single interrupt only
belong to this category. Also, almost all boards that require
multiple interrupts have their first interrupt classified as INTA.
- INTB:
In general, the second interrupt on add-in boards that require
multiple interrupts is classified as INTB. (Although this is not a
mandatory requirement.)
- INTC and INTD:
In general, the third interrupt on an add-in board is classified as
INTC and the fourth interrupt as INTD.
The PIIX4E PCI-ISA bridge has four programmable interrupt request (PIRQ) input
signals. All PCI interrupts (both on-board and PCI add-in boards) are connected to
one of these PIRQ signals. As only four signals are provided, some PCI interrupts are
physically merged on the CPU board and therefore share the same interrupt. The
table below lists the PIRQ signals and how these signals are connected to the on-board
PCI interrupts.
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