104 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9.1.1.7 I2S_COUNTER register
The I2S_COUNTER register counts the number of data samples written to the output (Left output +
Right output counts as 1). This can be used to control the audio decoder software.
9.1.1.8 I2S_SOCKET register
The I2S_SOCKET register specifies the LPP module socket IDs that are used as the data sources
for the Left and Right DMA channels. This is relevant only when the I2S interface is functioning in
DMA mode (I2S_CONFIG.DMA_MODE = 1).
9.1.1.9 I2S_ID register
The I2S_ID register is a read-only block ID register that can be used by the CPU to verify that the
I2S block is functioning.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
31:0 COUNTER RW R 0
Counter increments by one for every sample
written on output. Counts L+R as one sample in
stereo mode.
This counter will be reset to 0 when
I2S_CONFIG.ENABLE = 0
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
7:0 LEFT_SOCKET R RW 0
Socket number for left data samples
0–7: Supported
It is recommended that this value be set to 0.
15:8 RIGHT_SOCKET R RW 0
Socket number for right data samples
0–7: Supported
It is recommended that this value be set to 1.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
15:0 BLOCK_ID R 0x0000
A unique number identifying the block in the
memory space.
31:16 BLOCK_VERSION R 0x0001 Version number for the block.
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