108 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9.1.2.3 I2C_INTR register
The I2C_INTR register reports the status of I
2
C-related interrupt conditions. The interrupt status bits
correspond to status bits in the I2C_STATUS, but are sticky; that is, the interrupt status bit stays set
until cleared by firmware. The status bit is cleared when the current status changes.
9.1.2.4 I2C_INTR_MASK register
This register is used to enable/disable the reporting of specific I2C interrupt conditions to the ARM
CPU.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_DONE RW1S RW1C 0
Set when I2C_STATUS.RX_DONE
asserts, cleared by software.
1RX_DATA RW1SRW1C0
Set when I2C_STATUS.RX_DATA asserts,
cleared by software.
2 RX_HALF RW1S RW1C 0
Set when I2C_STATUS.RX_HALF asserts,
cleared by software.
3 TX_DONE RW1S RW1C 0
Set when I2C_STATUS.TX_DONE asserts,
cleared by software.
4 TX_SPACE RW1S RW1C 0
Set when I2C_STATUS.TX_SPACE
asserts, cleared by software.
5 TX_HALF RW1S RW1C 0
Set when I2C_STATUS.TX_HALF asserts,
cleared by software.
6TIMEOUT RW1SRW1C0
Set when I2C_STATUS.TIMEOUT asserts,
cleared by software.
7 LOST_ARBITRATION RW1S RW1C 0
Set when
I2C_STATUS.LOST_ARBITRATION
asserts, cleared by software.
8 ERROR RW1S RW1C 0
Set when I2C_STATUS.ERROR asserts,
cleared by software.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_DONE R RW 0 1: Report RX_DONE interrupt to CPU
1 RX_DATA R RW 0 1: Report RX_DATA interrupt to CPU
2 RX_HALF R RW 0 1: Report RX_HALF interrupt to CPU
3 TX_DONE R RW 0 1: Report TX_DONE interrupt to CPU
4 TX_SPACE R RW 0 1: Report TX_SPACE interrupt to CPU
5 TX_HALF R RW 0 1: Report TX_HALF interrupt to CPU
6 TIMEOUT R RW 0 1: Report TIMEOUT interrupt to CPU
7 LOST_ARBITRATION R RW 0
1: Report LOST_ARBITRATION interrupt
to CPU
8 ERROR R RW 0 1: Report ERROR interrupt to CPU
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