FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 109
FX3 Serial Peripheral Register Access
9.1.2.5 I2C_TIMEOUT register
This register specifies the bus timeout interval for I
2
C operations. This specifies the limit to which the
slave can delay a transfer by stretching the clock. Note that the timeout is specified in terms of the
I
2
C core clock, which is 10 times as fast as the I
2
C interface clock frequency specified.
9.1.2.6 I2C_DMA_TIMEOUT register
This register specifies the timeout interval before an I2C DMA transfer is failed with a TIMEOUT
error code. The interval is specified in terms of core clocks, which are 10X as fast as the interface
clock.
9.1.2.7 I2C_PREAMBLE_CTRL register
The data transfer between the FX3 and an I
2
C slave can be broken down into the preamble phase
and the data phase. The preamble phase consists of the I
2
C slave address, read/write bit, and any
device specific address bytes that precede the actual data transfer. The length of the preamble
phase in bytes depends on the I
2
C slave and direction of data transfer. The slave protocol may also
require start and stop conditions to be signaled at well defined positions within this preamble.
This register specifies the locations where the I
2
C interface should insert start and stop conditions
during a preamble transfer.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
31:0 TIMEOUT R RW 0xFFFFFFFF
Number of core clocks SCK can be held low
by the slave byte transmission before trig-
gering a timeout error.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
15:0 TIMEOUT16 R RW 0xFFFF
Number of core clocks DMA has to be not
ready before the condition is reported as
error condition.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
7:0 START R RW 0
If bit <x> is 1, issue a start after byte <x> of
the preamble.
15:8 STOP R RW 0
If bit <x> is 1, issue a stop after byte <x> of
the preamble.
If both START and STOP are set, STOP
takes priority.
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