112 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9.1.2.14 I2C_BYTES_TRANSFERRED register
This register indicates the number of bytes remaining to be transferred in the data phase. The I
2
C
block initializes this register with the I2C_BYTE_COUNT value and then counts down towards zero
as the transfer progresses.
9.1.2.15 I2C_SOCKET register
This register specifies the DMA socket numbers that should be used for read and write data trans-
fers through the I2C block, while in DMA mode.
9.1.2.16 I2C_ID register
Block ID register that the firmware can read to identify whether the block has been powered up.
9.1.2.17 I2C_POWER register
This register is used to power up or reset the I
2
C block in the FX3 device.
Bits Field Name
HW
Access
SW
Access
Default Value Description
31:0 BYTE_COUNT W R 0
Indicates number of bytes transferred in
the data phase so far. Does not include
preamble bytes.
Useful for determining when NACK hap-
pened during data transmission.
Bits Field Name
HW
Access
SW
Access
Default Value Description
7:0 EGRESS_SOCKET R RW 0
Socket number for egress data
0–7: Supported
This field should be set to 2.
15:8 INGRESS_SOCKET R RW 0
Socket number for ingress data
0–7: Supported
This field should be set to 5.
Bits Field Name
HW
Access
SW
Access
Default Value Description
15:0 BLOCK_ID R 0x0001
A unique number identifying the
block in the memory space.
31:16 BLOCK_VERSION R 0x0001 Version number for the block.
Bits Field Name
HW
Access
SW
Access
Default Value Description
0ACTIVE WR 0
Indicates whether the block is active.
Will be set to 0 for some time after the
block is reset, and will be set to 1
after the block has been fully pow-
ered up.
31 RESETN R RW 0
Active LOW reset signal for all logic
in the block.
After setting this bit to 1, firmware
polls and waits for the ‘active’ bit to
assert. Assert this bit ('0') for at least
10 µs for effective block reset.
To Next Page
Loading...