FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 115
FX3 Serial Peripheral Register Access
9.1.3.2 UART_STATUS register
This register reflects the current status of the UART block.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_DONE W R 0
Indicates receive operation completed, that
is, the desired length of data is received.
Only relevant when DMA_MODE = 1. Non
sticky.
1RX_DATA W R 0
Indicates data is available in the RX FIFO.
Only relevant when DMA_MODE = 0.
This bit is updated immediately after reads
from INGRESS_DATA register. Non sticky
2RX_HALF W R 0
Indicates that the RX FIFO is at least half
full.
This bit is updated immediately after reads
from INGRESS_DATA register. Non sticky
3 TX_DONE W R 0
Indicates no more data is available for
transmission. Non sticky.
If DMA_MODE = 0, this is defined as TX
FIFO empty and shift register empty.
If DMA_MODE = 1, this is defined as
BYTE_COUNT = 0 and shift register empty.
4 TX_SPACE W R 1
Indicates space is available in the TX FIFO.
This bit is updated immediately after writes
to EGRESS_DATA register. Non sticky.
5TX_HALF W R 1
Indicates that the TX FIFO is at least half
empty.
This bit is updated immediately after writes
to EGRESS_DATA register. Non sticky.
6CTS_STAT W R 0
CTS Status, polarity inverted from the pin.
CTS pin 0 ≥ CTS_STAT = 1; meaning that
FX3 can transmit.
Non sticky
7 CTS_TOGGLE RW1S RW1C 0 Set when CTS toggles.
8 BREAK W R 0
Break condition has been detected. Non
sticky.
9 ERROR RW1S RW1C 0
A protocol error has occurred with cause
ERROR_CODE. Must be cleared by soft-
ware. Sticky
27:24 ERROR_CODE W R 0xF
Error code, only relevant when ERROR = 1.
ERROR logs only the FIRST error to occur
and will never change value as long as
ERROR = 1.
0: Missing Stop bit
1: RX Parity error
12: TX FIFO overflow
13: RX FIFO underflow
14: RX FIFO overflow
15: No error
To Next Page
Loading...