116 FX3 Programmers Manual, Doc. # 001-64707 Rev. *C
FX3 Serial Peripheral Register Access
9.1.3.3 UART_INTR register
This register reports the status of various UART block interrupts on the FX3 device.
28 BUSY W R 0
Indicates the block is busy transmitting
data. This field may remain asserted after
the block is suspended and must be polled
before changing any configuration values.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_DONE RW1S RW1C 0
Set by hardware when
UART_STATUS.RX_DONE asserts, cleared
by software.
1 RX_DATA RW1S RW1C 0
Set by hardware when
UART_STATUS.RX_DATA asserts, cleared
by software.
2 RX_HALF RW1S RW1C 0
Set by hardware when
UART_STATUS.RX_HALF asserts, cleared
by software.
3 TX_DONE RW1S RW1C 0
Set by hardware when
UART_STATUS.TX_DONE asserts, cleared
by software.
4 TX_SPACE RW1S RW1C 0
Set by hardware when
UART_STATUS.TX_SPACE asserts, cleared
by software.
5 TX_HALF RW1S RW1C 0
Set by hardware when
UART_STATUS.TX_HALF asserts, cleared
by software.
6CTS_STAT RW1SRW1C0
Set by hardware when
UART_STATUS.CTS_STAT asserts, cleared
by software.
7 CTS_TOGGLE RW1S RW1C 0
Set by hardware when
UART_STATUS.CTS_TOGGLE asserts,
cleared by software.
8 BREAK RW1S RW1C 0
Set by hardware when
UART_STATUS.BREAK asserts, cleared by
software.
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
To Next Page
Loading...