DIGITAL-LOGIC Microspace MSM586SEN - Page 51

DIGITAL-LOGIC AG MSM586SEN/SEV Manual V1.5E
51
I/O Ad-
dress
Read/Write
Status
Description
000Ch W DMA clear byte pointer flip/flop
000Dh R DMA read temporary register
000Dh W DMA master clear
000Eh W DMA clear mask register
000Fh W DMA write mask register
0020h W Programmable Interrupt Controller - Initialization Command
Word 1 (ICW1) provided bit 4 = 1
bits 7-5 = 000 Used only in 8080 or 8085 mode
bit 4 = 1 ICW1 is used
bit 3 = 0 Edge triggered mode
1 Level triggered mode
bit 2 = 0 Successive interrupt vectors separated by
8 bytes
1 Successive interrupt vectors separated by
4 bytes
bit 1 = 0 Cascade mode
1 Single mode
bit 0 = 0 ICW4 not needed
1 ICW4 needed
0021h W Used for ICW2, ICW3, or ICW4 in sequential order af-
terICW1 is written to port 0020h
ICW2
bits 7-3 = Address A0-A3 of base vector address for
interrupt controller
bits 2-0 = Reserved (should be 000)
ICW3 (for slave controller 00A1h)
bits 7-3 = Reserved (should be 0000)
bits 2-0 = 1 Slave ID
ICW4
bits 7-5 = Reserved (should be 000)
bit 4 = 0 No special fully nested mode
1 Special fully nested mode
bits 3-2 = Mode
00 Non buffered mode
01 Non buffered mode
10 Buffered mode/slave
11 Buffered mode/master
bit 1 = 0 Normal EOI
1 Auto EOI
bit 0 = 0 8085 mode
1 8080 / 8088 mode
Continued...