Dwin T5L ASIC Series - Page 8

T5L_ASIC Development Guide
- 8 -
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D WI N T echnology
Pro f essional , Credi t able , Success f ul
GUI
71
P2.2
I/O port
SPI_CS
SPI Flash interface: chip selection
GUI
72
P2.3
I/O port
SPI_CLK
SPI Flash interface: clock
GUI
73
P2.4
I/O port
RTP_Y1
4-wire resistance touch screen
interface
CTP_SDA
Capacitance
touch screen
interface
GUI
74
P2.5
I/O port
RTP_X1
4-wire resistance touch screen
interface
CTP_INT
Capacitance
touch screen
interface
GUI
75
P2.6
I/O port
RTP_Y0
4-wire resistance touch screen
interface
CTP_SCL
Capacitance
touch screen
interface
GUI
76
P2.7
I/O port
RTP_X0
4-wire resistance touch screen
interface
CTP_RST
Capacitance
touch screen
interface
GUI
77
VDD
T5L1=1.25V
T5L2=1.2V
GUI
78
VIO
3.3V
GUI
79
P3.0
I/O port
CLK_OUT
System clock frequency division
output
GUI
80
P3.1
I/O port
FSK_TR
T/R switching signal for half-
duplex use of SFK transceiver
GUI
81
P3.2
I/O port
GUI
82
P3.3
I/O port
GUI
83
P3.4
I/O port
LCD_PCLK
LCD interface
GUI
84
P3.5
I/O port
LCD_DE
LCD interface
GUI
85
P3.6
I/O port
LCD_HS
LCD interface
GUI
86
P3.7
I/O port
LCD_VS
LCD interface
GUI
87
VDD
T5L1=1.25V
T5L2=1.2V
GUI
88
VIO
3.3V
GUI
89
P4.0
I/O port
LCD_B0
LCD interface
GUI
90
P4.1
I/O port
LCD_B1
LCD interface
GUI
91
P4.2
I/O port
LCD_B2
LCD interface
GUI
92
P4.3
I/O port
LCD_B3
LCD interface
GUI
93
P4.4
I/O port
LCD_B4
LCD interface
GUI
94
P4.5
I/O port
LCD_B5
LCD interface
GUI
95
P4.6
I/O port
LCD_B6
LCD interface
GUI
96
P4.7
I/O port
LCD_B7
LCD interface
GUI
97
VDD
T5L1=1.25V
T5L2=1.2V
GUI
98
VIO
3.3V
GUI
99
P5.0
I/O port
LCD_G0
LCD interface
GUI
100
P5.1
I/O port
LCD_G1
LCD interface
GUI
101
P5.2
I/O port
LCD_G2
LCD interface