Reproduction forbidden without Fibocom Wireless Inc. written authorization - All Rights Reserved.
L850-GL Hardware User Manual Page 31 of 54
Pin# Pin Name I/O Reset Value Description Type
52 CLKREQ# O T
Asserted by device to request a PCIe
reference clock be available (active clock
state) in order to transmit data. It also used by
L1 PM Sub states mechanism, asserted by
either host or device to initiate an L1 exit.
Active low, internal pull up(10KΩ)
CMOS 3.3V
54 PEWAKE# O L
Asserted to wake up system and reactivate
PCIe link from L2 to L0, it depends on system
whether supports wake up functionality.
Active low, open drain output and should add
external pull up on platform
CMOS 3.3V
3.4.1.2 PCIe Interface Application
The reference circuit is shown in Figure 3-11:
Figure 3-11 Reference Circuit for PCIe Interface
L850 module supports one PCIe 1.0 interface, including three difference pairs: transmit pair TXP/N,
receiving pair RXP/N and clock pair CLKP/N.
PCIe can achieve the maximum transmission rate of 2.5 GT/s, and must strictly follow the rules below in
PCB Layout:
The differential signal pair lines shall be parallel and equal in length;
The differential signal pair lines shall be short if possible and be controlled within 15 inch(380
mm) for AP end;
The impedance of differential signal pair lines is recommended to be 100 ohm, and can be
controlled to 80～120 ohm in accordance with PCIe protocol;
To Next Page
