FriendlyARM Mini210S - Tiny210 CPU Board Interface and Port; Jtag

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CON1.27
Xmmc3DATA2/Xmmc2DATA6
CON1.28
CAM_B_VSYNC
CON1.29
Xmmc3DATA3/Xmmc2DATA7
CON1.30
CAM_B_HREF
CON1.31
Xi2sCLK1/PCM_SCLK1/AC97_BITCLK
CON1.32
CAM_B_FIELD
CON1.33
Xi2sCDCLK1/PCM_EXTCLK1/AC97_RESETn
CON1.34
CAM_B_CLKOUT
CON1.35
Xi2sLRCK1/PCM_FSYNC1/AC97_SYNC
CON1.36
CAMERA_B_GPIO0
CON1.37
Xi2sSDI1/PCM_SIN1/AC97_SDI
CON1.38
CAMERA_B_GPIO1
CON1.39
Xi2sSDO1/PCM_SOUT1/AC97_SDO
CON1.40
CAMERA_B_GPIO2
CON1.41
XpcmSCLK0/SPDIF_OUT0/Xi2sSCLK2
CON1.42
CAM_B_RESET
CON1.43
XpcmEXTCLK0/SPDIF_EXTCLK/Xi2sCDCLK2
CON1.44
Xi2cSCL1
CON1.45
XpcmFSYNC0/LCD_FRM/Xi2sLRCK2
CON1.46
Xi2cSDA1
CON1.47
XpcmSIN0/Xi2sSDI2
CON1.48
XpwmTOUT2
CON1.49
XpcmSOUT0/Xi2sSDO2
CON1.50
XpwmTOUT3/PWM_MIE
CON1.51
GND
CON2
Spec
CON2
Spec
CON2.1
Xi2cSDA0
CON2.2
Xi2cSCL0
CON2.3
CAMERA_A_GPIO2
CON2.4
CAM_A_RESET
CON2.5
XciCLKenb
CON2.6
XciHREF
CON2.7
XciVSYNC
CON2.8
XciPCLK
CON2.9
XciYDATA7
CON2.10
XciYDATA6
CON2.11
XciYDATA5
CON2.12
XciYDATA4
CON2.13
XciYDATA3
CON2.14
XciYDATA2
CON2.15
XciYDATA1
CON2.16
XciYDATA0
CON2.17
VDD_SYS_3.3V
CON2.18
VDD_CAM_2.8V
CON2.19
VDD_CAM_1.8V
CON2.20
DGND
CON2.21
Xi2cSDA2/IEM_SCLK
CON2.22
XEINT15
CON2.23
Xi2cSCL2/IEM_SPWI
CON2.24
XEINT14
CON2.25
XvVD0
CON2.26
XvVD1
CON2.27
XvVD8
CON2.28
XvVD9
CON2.29
XvVD16
CON2.30
XvVD17
1.1.3 Tiny210 CPU Board Interface and Port
1.1.3.1 JTAG
The Tiny210 CPU board has test points for JTAG as follows: GND, TDO, TDI, TCK,
TMS, TSRT and 3.3V: